View STM32F217ZGT6_6608427.PDF datasheet online --- IC-ON-LINE

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this is information on a product in full production. october 2012 doc id 17050 rev 8 1/173 1 stm32f215xx stm32f217xx arm-based 32-bit mcu, 150dmips, up to 1 mb flash/128+4kb ram, crypto, usb otg hs/fs, ethernet, 17 tims, 3 adcs, 15 comm. interfaces & camera datasheet ? production data features core: arm 32-bit cortex?-m3 cpu (120 mhz max) with adaptive real -time accelerator (art accelerator?) allowing 0-wait state execution performance from flash memory, mpu, 150 dmips/1.25 dmips/mhz (dhrystone 2.1) memories ? up to 1 mbyte of flash memory ? 512 bytes of otp memory ? up to 128 + 4 kbytes of sram ? flexible static memory controller that supports compact flash, sram, psram, nor and nand memories ? lcd parallel interface, 8080/6800 modes crc calculation unit clock, reset and supply management ? from 1.8 to 3.6 v application supply+i/os ? por, pdr, pvd and bor ? 4 to 26 mhz crystal oscillator ? internal 16 mhz factory-trimmed rc ? 32 khz oscillator for rtc with calibration ? internal 32 khz rc with calibration low power ? sleep, stop and standby modes ?v bat supply for rtc, 20 32 bit backup registers, and optional 4 kb backup sram 3 12-bit, 0.5 s adcs with up to 24 channels and up to 6 msps in tr iple interleaved mode 2 12-bit d/a converters general-purpose dma: 16-stream controller with centralized fifos and burst support 96-bit unique id up to 17 timers ? up to twelve 16-bit and two 32-bit timers, up to 120 mhz, each with up to 4 ic/oc/pwm or pulse counter and quadrature (incremental) encoder input debug mode: serial wire debug (swd), jtag, and cortex-m3 embedded trace macrocell? up to 140 i/o ports with interrupt capability: ? up to 136 fast i/os up to 60 mhz ? up to 138 5 v-tolerant i/os up to 15 communication interfaces ? up to 3 i 2 c interfaces (smbus/pmbus) ? up to 4 usarts and 2 uarts (7.5 mbit/s, iso 7816 interface, lin, irda, modem control) ? up to 3 spis (30 mbit/s), 2 with muxed i 2 s to achieve audio class accuracy via audio pll or external pll ? 2 can interfaces (2.0b active) ? sdio interface advanced connectivity ? usb 2.0 full-speed device/host/otg controller with on-chip phy ? usb 2.0 high-speed/full-speed device/host/otg controller with dedicated dma, on-chip full-speed phy and ulpi ? 10/100 ethernet mac with dedicated dma: supports ieee 1588v2 hardware, mii/rmii 8- to 14-bit paralle l camera interface (48 mbyte/s max) cryptographic acceleration ? hardware acceleration for aes 128, 192, 256, triple des, hash (md5, sha-1) ? analog true random number generator analog true random number generator table 1. device summary reference part number stm32f215xx stm32f215rg, stm32f215vg, stm32f215zg, stm32f215re, stm32f215ve, stm32f215ze stm32f217xx stm32f217vg, stm32f217ig, stm32f217zg, stm32f217ve, stm32f217ie, stm32f217ze lqfp64 (10 10 mm) lqfp100 (14 14 mm) lqfp144 (20 20 mm) lqfp176 (24 24 mm) fbga ufbga176 (10 10 mm) www.st.com
contents stm32f21xxx 2/173 doc id 17050 rev 8 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.1 arm ? cortex?-m3 core with embedded flash and sram . . . . . . . . . 17 2.2.2 adaptive real-time memory accelerator (art accelerator?) . . . . . . . . 17 2.2.3 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.4 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.5 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 18 2.2.6 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.7 multi-ahb bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.8 dma controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.9 flexible static memory controller (fsmc) . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.10 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 20 2.2.11 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.12 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.13 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.14 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.15 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.16 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.17 real-time clock (rtc), backup sram and backup registers . . . . . . . . 23 2.2.18 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.19 v bat operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.20 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.21 inter-integrated circuit interface (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.2.22 universal synchronous/asynchronous receiver transmitters (uarts/usarts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.2.23 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.2.24 inter-integrated sound (i 2 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.2.25 sdio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.26 ethernet mac interface with dedicated dma and ieee 1588 support . 29 2.2.27 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.28 universal serial bus on-the-go full-speed (otg_fs) . . . . . . . . . . . . . . . 30
stm32f21xxx contents doc id 17050 rev 8 3/173 2.2.29 universal serial bus on-the-go high-speed (otg_hs) . . . . . . . . . . . . . 30 2.2.30 audio pll (plli2s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.31 digital camera interface (dcmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.32 cryptographic acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2.33 true random number generator (rng) . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2.34 gpios (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.35 adcs (analog-to-digital converters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.36 dac (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.37 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.38 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.39 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.2 vcap1/vcap2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.3.3 operating conditions at power-up / power-down (regulator on) . . . . . . 66 5.3.4 operating conditions at power-up / power-down (regulator off) . . . . . 66 5.3.5 embedded reset and power control block characteristics . . . . . . . . . . . 67 5.3.6 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3.7 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3.8 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.3.9 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.3.10 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
contents stm32f21xxx 4/173 doc id 17050 rev 8 5.3.11 pll spread spectrum clock generation (sscg) characteristics . . . . . . 88 5.3.12 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3.13 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.3.14 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 93 5.3.15 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.3.16 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.3.17 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3.18 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.3.19 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.3.20 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.3.21 dac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 5.3.22 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.3.23 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.3.24 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.3.25 fsmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.3.26 camera interface (dcmi) timing specifications . . . . . . . . . . . . . . . . . . 140 5.3.27 sd/sdio mmc card host interface (sdio) characteristics . . . . . . . . . 140 5.3.28 rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 appendix a application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 a.1 main applications versus package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 a.2 application example with regulator off . . . . . . . . . . . . . . . . . . . . . . . . . 154 a.3 usb otg full speed (fs) interface solutions . . . . . . . . . . . . . . . . . . . . . 154 a.4 usb otg high speed (hs) interface solutions . . . . . . . . . . . . . . . . . . . . 156 a.5 complete audio player solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 a.6 ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
stm32f21xxx list of tables doc id 17050 rev 8 5/173 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f215xx and stm32f217xx: features and peripheral counts. . . . . . . . . . . . . . . . . . 12 table 3. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 4. usart feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 5. stm32f21x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 6. fsmc pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 7. alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 8. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 9. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 10. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 11. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 12. limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 63 table 13. vcap1/vcap2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 14. operating conditions at power-up / power-down (regulator on) . . . . . . . . . . . . . . . . . . . . 66 table 15. operating conditions at power-up / power-down (regulator off). . . . . . . . . . . . . . . . . . . . 66 table 16. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 17. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 18. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabled) or ram . . . . . . . . . . . . . . . . . . . 70 table 19. typical and maximum current consumption in sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 73 table 20. typical and maximum current consumptions in stop mode . . . . . . . . . . . . . . . . . . . . . . . . 75 table 21. typical and maximum current consumptions in standby mode . . . . . . . . . . . . . . . . . . . . . 76 table 22. typical and maximum current consumptions in v bat mode. . . . . . . . . . . . . . . . . . . . . . . . 76 table 23. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 24. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 25. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 26. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 27. hse 4-26 mhz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 table 28. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 29. hsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 30. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 31. main pll characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 32. plli2s (audio pll) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 33. sscg parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 34. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 35. flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 36. flash memory programming with v pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 37. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 38. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 39. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 40. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 41. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 42. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 43. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 44. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 45. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 46. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
list of tables stm32f21xxx 6/173 doc id 17050 rev 8 table 47. characteristics of timx connected to the apb1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 48. characteristics of timx connected to the apb2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 49. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 50. scl frequency (f pclk1 = 30 mhz.,v dd = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 51. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 52. i 2 s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 53. usb otg fs startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 54. usb otg fs dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 55. usb otg fs electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 56. usb hs dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 0 table 57. clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 58. ulpi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 59. ethernet dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 60. dynamics characteristics: ethernet mac signals for smi. . . . . . . . . . . . . . . . . . . . . . . . . 112 table 61. dynamics characteristics: ethernet mac signals for rmii . . . . . . . . . . . . . . . . . . . . . . . . 112 table 62. dynamics characteristics: ethernet mac signals for mii . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 63. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 64. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 65. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 66. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 67. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 68. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 69. asynchronous non-multiplexed sram/psram/nor read timings . . . . . . . . . . . . . . . . . 123 table 70. asynchronous non-multiplexed sram/psram/nor write timings . . . . . . . . . . . . . . . . . 124 table 71. asynchronous multiplexed psram/nor read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 72. asynchronous multiplexed psram/nor write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 73. synchronous multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 74. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 75. synchronous non-multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . 130 table 76. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 77. switching characteristics for pc card/cf read and write cycles in attribute/common space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 78. switching characteristics for pc card/cf read and write cycles in i/o space . . . . . . . . . 137 table 79. switching characteristics for nand flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 80. switching characteristics for nand flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 81. dcmi characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 82. sd / mmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 83. rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 84. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 143 table 85. lqpf100 ? 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 145 table 86. lqfp144 20 x 20 mm, 144-pin low-profile quad flat package mechanical data. . . . . . . . 146 table 87. lqfp176 - low profile quad flat package 24 24 1.4 mm package mechanical data . 148 table 88. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm mechanical data . 150 table 89. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 90. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 91. main applications versus package for stm32f2xxx microcontrollers . . . . . . . . . . . . . . . 153 table 92. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
stm32f21xxx list of figures doc id 17050 rev 8 7/173 list of figures figure 1. compatible board design between stm32f10xx and stm32f2xx for lqfp64 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 figure 2. compatible board design between stm32f10xx and stm32f2xx for lqfp100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3. compatible board design between stm32f10xx and stm32f2xx for lqfp144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 4. stm32f21x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. multi-ahb matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. startup in regulator off: slow v dd slope - power-down reset risen after v cap_1 /v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 7. startup in regulator off: fast v dd slope - power-down reset risen before v cap_1 /v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 23 figure 8. stm32f21x lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 9. stm32f21x lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 10. stm32f21x lqfp144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 11. stm32f21x lqfp176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 12. stm32f21x ufbga176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9 figure 13. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 14. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 15. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 16. power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 17. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 18. number of wait states versus f cpu and v dd range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 19. external capacitor c ext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 20. typical current consumption vs temperature, run mode, code with data processing running from ram, and peripherals on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 21. typical current consumption vs temperature, run mode, code with data processing running from ram, and peripherals off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 22. typical current consumption vs temperature, run mode, code with data processing running from flash, art accelerator off, peripherals on . . . . . . . . . . . . . . . 72 figure 23. typical current consumption vs temperature, run mode, code with data processing running from flash, art accelerator off, peripherals off . . . . . . . . . . . . . . 72 figure 24. typical current consumption vs temperature in sleep mode, peripherals on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 25. typical current consumption vs temperature in sleep mode, peripherals off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 26. typical current consumption vs temperature in stop mode . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 27. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 28. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 29. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 30. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 31. acc hsi versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 32. acc lsi versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 33. pll output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 34. pll output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 35. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 36. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 37. i 2 c bus ac waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
list of figures stm32f21xxx 8/173 doc id 17050 rev 8 figure 38. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 39. spi timing diagram - slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 40. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 06 figure 41. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 42. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 43. usb otg fs timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 110 figure 44. ulpi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 45. ethernet smi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 46. ethernet rmii timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 47. ethernet mii timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 48. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 49. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 50. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . 118 figure 51. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . 118 figure 52. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 53. asynchronous non-multiplexed sram/psram/nor read waveforms . . . . . . . . . . . . . . 123 figure 54. asynchronous non-multiplexed sram/psram/nor write waveforms . . . . . . . . . . . . . . 124 figure 55. asynchronous multiplexed psram/nor read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 125 figure 56. asynchronous multiplexed psram/nor write waveforms . . . . . . . . . . . . . . . . . . . . . . . 126 figure 57. synchronous multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 58. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 59. synchronous non-multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 60. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 61. pc card/compactflash controller waveforms for common memory read access . . . . . . 132 figure 62. pc card/compactflash controller waveforms for common memory write access . . . . . . 133 figure 63. pc card/compactflash controlle r waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 64. pc card/compactflash controlle r waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 65. pc card/compactflash controller waveforms for i/o space read access . . . . . . . . . . . . 135 figure 66. pc card/compactflash controller waveforms for i/o space write access . . . . . . . . . . . . 136 figure 67. nand controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 68. nand controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 69. nand controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 139 figure 70. nand controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 139 figure 71. sdio high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 72. sd default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 figure 73. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 143 figure 74. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 75. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 144 figure 76. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 77. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 78. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 79. lqfp176 - low profile quad flat package 24 24 1.4 mm, package outline . . . . . . . . 148 figure 80. lqfp176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 81. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm, package outline . 150 figure 82. regulator off/internal reset on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 83. usb otg fs (full speed) device-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 84. usb otg fs (full speed) host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 85. otg fs (full speed) connection dual-role with internal phy . . . . . . . . . . . . . . . . . . . . . . 155 figure 86. otg hs (high speed) device connection, host and dual-role
stm32f21xxx list of figures doc id 17050 rev 8 9/173 in high-speed mode with external phy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 87. complete audio player solution 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 88. complete audio player solution 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 89. audio player solution using pll, plli2s, usb and 1 crystal . . . . . . . . . . . . . . . . . . . . . . 158 figure 90. audio pll (plli2s) providing accurate i2s clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 91. master clock (mck) used to drive the external audio dac. . . . . . . . . . . . . . . . . . . . . . . . 159 figure 92. master clock (mck) not used to drive the external audio dac. . . . . . . . . . . . . . . . . . . . . 159 figure 93. mii mode using a 25 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 94. rmii with a 50 mhz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 95. rmii with a 25 mhz crystal and phy with pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
introduction stm32f21xxx 10/173 doc id 17050 rev 8 1 introduction this datasheet provides the description of the stm32f215xx and stm32f217xx lines of microcontrollers. for more details on the whole stmicroelectronics stm32? family, please refer to section 2.1: full compatibility throughout the family . the stm32f215xx and stm32f217xx datasheet should be read in conjunction with the stm32f20x/stm32f21x re ference manual. they will be refe rred to as stm32f21x devices throughout the document. for information on programming, erasing and protection of the internal flash memory, please refer to the stm32f20x/stm32f21x flash programming manual (pm0059). the reference and flash programming manuals are both available from the stmicroelectronics website www.st.com . for information on the cortex?-m3 core please refer to the cortex?-m3 technical reference manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
stm32f21xxx description doc id 17050 rev 8 11/173 2 description the stm32f21x family is based on the high-performance arm ? cortex?-m3 32-bit risc core operating at a frequency of up to 120 mhz. the family incorporates high-speed embedded memories (flash memory up to 1 mbyte, up to 128 kbytes of system sram), up to 4 kbytes of backup sram, and an extensive range of enhanced i/os and peripherals connected to two apb buses, three ahb bu ses and a 32-bit multi-ahb bus matrix. the devices also feature an adaptive real-time memory accelerator (art accelerator?) which allows to achieve a performance equivalent to 0 wait state program execution from flash memory at a cpu frequency up to 120 mhz. this performance has been validated using the coremark benchmark. all devices offer three 12-bit adcs, two dacs, a low-power rtc, twelve general-purpose 16-bit timers including two pwm timers for motor control, two general-purpose 32-bit timers. a true number random generator (rng). they also feature standard and advanced communication interfaces. new advanced peripherals include an sdio, an enhanced flexible static memory control (fsmc) interface (for devices offered in packages of 100 pins and more), a cryptographic acceleration cell, and a camera interface for cmos sensors. the devices also feature standard peripherals. up to three i 2 cs three spis, two i 2 ss. to achieve audio class accuracy, the i 2 s peripherals can be clocked via a dedicated internal audio pll or via an external pll to allow synchronization. 4 usarts and 2 uarts a usb otg high-speed with full- speed capability (with the ulpi) a second usb otg (full-speed) tw o c a n s an sdio interface ethernet and camera interface available on stm32f217xx devices only. the stm32f215xx and stm32f217xx devices operate in the ?40 to +105 c temperature range from a 1.8 v to 3.6 v power supply. a comprehensive set of power-saving modes allow the design of low-power applications. stm32f215xx and stm32f217xx devices are offered in various packages ranging from 64 pins to 176 pins. the set of included perip herals changes with the device chosen.these features make the stm32f215xx and stm32f217xx microcontroller family suitable for a wide range of applications: motor drive and application control medical equipment industrial applications: plc, inverters, circuit breakers printers, and scanners alarm systems, video intercom, and hvac home audio appliances figure 4 shows the general block diagram of the device family.
description stm32f21xxx 12/173 doc id 17050 rev 8 table 2. stm32f215xx and stm32f217xx: features and peripheral counts peripherals stm32f215rx stm32f215vx stm32f 215zx stm32f217vx stm32f217zx stm32f217ix flash memory in kbytes 512 1024 512 1024 512 1024 512 1024 512 1024 512 1024 sram in kbytes system 128(112+16) backup 4 4 4 4 4 4 fsmc memory controller no ye s (1) ethernet (2) no ye s timers general-purpose 10 advanced-control 2 basic 2 iwdg ye s wwdg ye s rtc ye s random number generator ye s communication interfaces spi / (i 2 s) 3 (2) (3) i 2 c 3 usart uart 4 2 usb otg fs ye s usb otg hs ye s can 2 camera interface (2) no ye s encryption ye s gpios 51 82 114 82 114 140 sdio ye s 12-bit adc number of channels 3 16 16 24 16 24 24 12-bit dac number of channels ye s 2 maximum cpu frequency 120 mhz operating voltage 1.8 v to 3.6 v
stm32f21xxx description doc id 17050 rev 8 13/173 operating temperatures ambient temperatures: ?40 to +85 c /?40 to +105 c junction temperature: ?40 to + 125 c package lqfp64 lqfp100 lqfp144 lqfp100 lqfp144 ufbga176, lqfp176 1. for the lqfp100 package, only fsmc bank1 or bank2 are available. bank1 can only support a multip lexed nor/psram memory using th e ne1 chip select. bank2 can only support a 16- or 8- bit nand flash memory using the nce2 chip select. the interrupt lin e cannot be used since port g is not available in this packa ge. 2. camera interface and ethernet are av ailable only in st m32f217x devices. 3. the spi2 and spi3 interfaces give the flex ibility to work in an exclusive way in either the spi mode or the i2s audio mode. table 2. stm32f215xx and stm32f217xx: features and peripheral counts (continued) peripherals stm32f215rx stm32f215vx stm32f 215zx stm32f217vx stm32f217zx stm32f217ix
description stm32f21xxx 14/173 doc id 17050 rev 8 2.1 full compatibility throughout the family the stm32f215xx and stm32f217xx constitute the stm32f21x family whose members are fully pin-to-pin, software and feature compatible, allowing the user to try different memory densities and peripherals for a greater degree of freedom during the development cycle. the stm32f215xx and stm32f 217xx devices maintain a close compatibility with the whole stm32f10xxx family. all functional pins are pin-to-pin compatible. the stm32f215xx and stm32f217xx, however, are not drop-in replacements for the stm32f10xxx devices: the two families do not have the same power scheme, and so their power pins are different. nonetheless, transition from the stm32f10xxx to the stm32f21x family remains simple as only a few pins are impacted. figure 3 and figure 1 provide compatible board designs between the stm32f21x and the stm32f10xxx family. figure 1. compatible board design between stm32f10xx and stm32f2xx for lqfp64 package 3 1 116 17 3 2 33 4 8 64 49 47 v ss v ss v ss v ss 0 re s i s tor or s oldering b ridge pre s ent for the s tm 3 2f10xx config u r a tion, not pre s ent in the s tm 3 2f2xx config u r a tion a i15962 b
stm32f21xxx description doc id 17050 rev 8 15/173 figure 2. compatible board design between stm32f10xx and stm32f2xx for lqfp100 package figure 3. compatible board design between stm32f10xx and stm32f2xx for lqfp144 package 1. rfu = reserved for future use. ai15961c 20 49 125 26 50 51 75 100 76 73 19 v ss v ss v dd v ss v ss v ss 0 resistor or soldering bridge present for the stm32f10xx configuration, not present in the stm32f2xx configuration 99 (rfu) v ss v dd v ss for stm32f10xx v dd for stm32f2xx two 0 resistors connected to: - v ss for the stm32f10xx - v dd , v ss , or nc for the stm32f2xx ai15960c 31 71 136 37 72 73 108 144 109 v ss 0 resistor or soldering bridge present for the stm32f10xx configuration, not present in the stm32f2xx configuration 106 v ss 30 two 0 resistors connected to: v ss v dd v ss v ss 143 (rfu) v ss v dd - v ss for the stm32f10xx - v dd , v ss , or nc for the stm32f2xx
description stm32f21xxx 16/173 doc id 17050 rev 8 2.2 device overview figure 4. stm32f21x block diagram 1. the timers connected to apb2 are clock ed from timxclk up to 120 mhz, while the timers connected to apb1 are clocked from timxclk up to 60 mhz. 2. the camera interface and ethernet ar e available only in stm32f217xx devices. gpio port a ahb/apb2 ext it. wkup 140 af pa[15:0] gpio port b pb[15:0] tim1 / pwm 4 compl. channels (tim1_ch[1:4]n ) 4 channels (tim1_ch[1:4]) , etr, bkin as af tim8 / pwm gpio port c pc[15:0] usart 1 rx, tx, ck, cts, rts as af gpio port d pd[15:0] gpio port e pe[15:0] gpio port f pf[15:0] gpio port g pg[15:0] spi1 mosi, miso sck, nss as af apb2 60mhz apb1 30mhz 8 analog inputs common to the 3 adcs 8 analog inputs common to the adc1 & 2 v ddref_adc 8 analog inputs to adc3 4 channels, etr as af 4 channels, etr as af 4 channels, etr as af 4 channels rx, tx, ck, usart2 rx, tx, ck usart3 rx, tx as af uart4 rx, tx as af uart5 mosi/dout, miso/din, sck/ck spi2/i2s2 nss/ws, mck as af mosi/dout, miso/din, sck/ck spi3/i2s3 nss/ws, mck as af scl, sda, smba as af i2c1/smbus scl, sda, smba as af i2c2/smbus tx, rx bxcan1 tx, rx bxcan2 dac1_out as af dac2_out as af itf wwdg 4 kb bkspram rtc_af1 osc32_in osc_in osc_out osc32_out nrst v dda , v ssa v cap1, v cap2 usart 6 rx, tx, ck, cts, rts as af smcard irda smcard irda smcard irda smcard irda 16b 16b 32b 16b 16b 32b 16b 16b cts, rts as af cts, rts as af sdio / mmc d[7:0] cmd, ck as af v bat = 1.65 to 3.6 v dma1 ahb/apb1 dma2 scl, sda, smba as af i2c3/smbus gpio port h ph[15:0] gpio port i pi[11:0] jtag & sw arm cortex-m3 120 mhz art accelerator d-bus s-bus i-bus nvic etm mpu njtrst, jtdi, jtdo/swd, jtdo traceclk traced[3:0] jtck/swclk ethernet mac dma/ mii or rmii as af mdio as af fifo 10/100 usb dma/ fifo otg hs dp, dm ulpi: ck, d(7:0), dir, stp, nxt dma2 8 streams fifo dma1 8 streams fifo accel/ cache sram 112 kb sram 16 kb clk, ne [3:0], a[23:0] d[31:0], oen, wen, nbl[3:0], nl, nreg nwait/iordy, cd niord, iowr, int[2:3] intn, niis16 as af scl, sda, intn, id, vbus, sof fifo tdes, aes256 fifo hash rng camera interface hsync, vsync pixclk, d[13:0] usb phy otg fs dp dm fifo fifo ahb1 120 mhz phy fifo usart 2mbps temperature sensor adc1 adc2 adc 3 if if @vdda @vdda por/pdr/ supply @vdda supervision pvd reset int p or xtal osc 4-26 mhz xtal 32 khz hclkx managt rtc rc hs fclk rc ls standby iwdg @v bat @vdda @vdd awu reset & clock control pll1&2 pclkx interface v dd = 1.8 to 3.6 v v ss voltage regulator 3.3 v to 1.2 v v dd12 power managmt @vdd rtc_af1 backup register scl/sda, intn, id, vbus, sof ahb bus-matrix 8s7m apb2 60mhz ahb2 120 mhz ls ls 2 channels as af 1 channel as af 1 channel as af tim14 16b 16b 16b tim9 2 channels as af tim10 1 channel as af 16b 16b tim11 1 channel as af 16b bor dac1 dac2 flash 1 mbyte sram, psram, nor flash, pc card (ata), nand flash external memory controller (fsmc) tim6 tim7 tim2 tim3 tim4 tim5 tim12 tim13 ai15968d 4 compl. channels (tim1_ch[1:4]n ) 4 channels (tim1_ch[1:4]) , etr, bkin as af fifo apb1 30mhz ahb3
stm32f21xxx description doc id 17050 rev 8 17/173 2.2.1 arm ? cortex?-m3 core with embedded flash and sram the arm cortex-m3 processor is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm cortex-m3 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. with its embedded arm core, the stm32f21x family is compatible with all arm tools and software. figure 4 shows the general block diagram of the stm32f21x family. 2.2.2 adaptive real-time memory accelerator (art accelerator?) the art accelerator? is a memory accelera tor which is optimized for stm32 industry- standard arm ? cortex?-m3 processors. it balances the inherent performance advantage of the arm cortex-m3 over flash memory technologies, which normally requires the processor to wait for the flash memory at higher operating frequencies. to release the processor full 150 dmips performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache which increases program execution speed from the 128-bit flash memory. based on coremark benchmark, the performance achieved thanks to the art accelerator is equivalent to 0 wait state program execution from flash memory at a cpu frequency up to 120 mhz. 2.2.3 memory protection unit the memory protection unit (mpu) is used to manage the cpu accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. this memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the mpu is especially helpful fo r applications where some critic al or certified code has to be protected against the misbehavior of other tasks. it is usually managed by an rtos (real- time operating system). if a program accesses a memory location that is prohibited by the mpu, the rtos can detect it and take action. in an rtos environment, the kernel can dynamically update the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it. 2.2.4 embedded flash memory the stm32f21x devices embed a 128-bit wide flash memory of 128 kbytes, 256 kbytes, 512 kbytes, 768 kbytes or 1 mbytes available for storing programs and data. the devices also feature 512 bytes of otp memory that can be used to store critical user data such as ethernet mac addresses or cryptographic keys.
description stm32f21xxx 18/173 doc id 17050 rev 8 2.2.5 crc (cyclic redundanc y check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 2.2.6 embedded sram all stm32f21x products embed: up to 128 kbytes of system sram accessed (read/write) at cpu clock speed with 0 wait states 4 kbytes of backup sram. the content of this area is protected against possible unwanted write accesses, and is retained in standby or v bat mode. 2.2.7 multi-ahb bus matrix the 32-bit multi-ahb bus matrix interconnects all the masters (cpu, dmas, ethernet, usb hs) and the slaves (flash memory, ram, fsmc, ahb and apb peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. figure 5. multi-ahb matrix arm cortex-m3 gp dma1 gp dma2 mac ethernet usb otg hs bus matrix-s s0 s1 s2 s3 s4 s5 s6 s7 icode dcode art accel. flash memory sram 112 kbyte sram 16 kbyte ahb1 periph ahb2 periph fsmc static memctl m0 m1 m2 m3 m4 m5 m6 i-bus d-bus s-bus dma_p1 dma_mem1 dma_mem2 dma_p2 ethernet_m usb_hs_m ai15963c apb1 apb2
stm32f21xxx description doc id 17050 rev 8 19/173 2.2.8 dma controller (dma) the devices feature two general-purpose dual-port dmas (dma1 and dma2) with 8 streams each. they are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. they share some centralized fifos for apb/ahb peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (ahb/apb). the two dma controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. the two dma controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. each stream is connected to dedicated hardware dma requests, with support for software trigger on each stream. configuration is made by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi and i 2 s i 2 c usart and uart general-purpose, basic and advanced-control timers timx dac sdio cryptographic acceleration camera interface (dcmi) adc. 2.2.9 flexible static memory controller (fsmc) the fsmc is embedded in all stm32f21x devices. it has four chip select outputs supporting the following modes: pc card/compact flash, sram, psram, nor flash and nand flash. functionality overview: write fifo code execution from external memory except for nand flash and pc card maximum frequency (f hclk ) for external access is 60 mhz lcd parallel interface the fsmc can be configured to interface seamlessly with most graphic lcd controllers. it supports the intel 8080 and motorola 6800 modes, and is flexible enough to adapt to specific lcd interfaces. this lcd parallel interface capability makes it easy to build cost- effective graphic applications using lcd modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration.
description stm32f21xxx 20/173 doc id 17050 rev 8 2.2.10 nested vectored inte rrupt controller (nvic) the stm32f21x devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the cortex?-m3. the nvic main features are the following: closely coupled nvic gives low-latency interrupt processing interrupt entry vector table address passed directly to the core closely coupled nvic core interface allows early processing of interrupts processing of late arriving, higher-priority interrupts support tail chaining processor state automatically saved interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimum interrupt latency. 2.2.11 external interr upt/event controller (exti) the external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal apb2 cloc k period. up to 140 gp ios can be connected to the 16 external interrupt lines. 2.2.12 clocks and startup on reset the 16 mhz internal rc oscillator is select ed as the default cpu clock. the 16 mhz internal rc oscillator is factory-trimme d to offer 1% accura cy. the application can then select as system clock either the rc os cillator or an external 4-26 mhz clock source. this clock is monitored for failu re. if failure is detected, the system automatically switches back to the internal rc oscillator and a software interrupt is generated (i f enabled). similarly, full interrupt management of the pll clock entry is available when necessary (for example if an indirectly used ex ternal oscillator fails). the advanced clock controller clocks the core and all peripherals using a single crystal or oscillator. in particular, the ethernet and usb otg fs peripherals can be clocked by the system clock. several prescalers and plls allow the configuration of the three ahb buses, the high-speed apb (apb2) and the low-speed apb (apb1) domain s. the maximum frequ ency of the three ahb buses is 120 mhz and the maximum frequency the high-speed apb domains is 60 mhz. the maximum allowed frequen cy of the low-speed apb domain is 30 mhz. the devices embed a dedicate pll (plli2s) which allow to achieve audio class performance. in this case, the i 2 s master clock can generate all standard sampling frequencies from 8 khz to 192 khz.
stm32f21xxx description doc id 17050 rev 8 21/173 2.2.13 boot modes at startup, boot pins are used to select one out of three boot options: boot from user flash boot from system memory boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1 (pa9/pa10), usart3 (pc10/pc 11 or pb10/pb11), can2 (pb5/pb13), usb otg fs in device mode (pa11/pa12) through dfu (device firmware upgrade). 2.2.14 power supply schemes v dd = 1.8 to 3.6 v: external power supply for i/os and the internal regulator (when enabled), provided externally through v dd pins. v ssa , v dda = 1.8 to 3.6 v: external analog power supplies for adc, dac, reset blocks, rcs and pll. v dda and v ssa must be connected to v dd and v ss , respectively. v bat = 1.65 to 3.6 v: power supply for rtc, external clock, 32 khz oscillator and backup registers (through power switch) when v dd is not present. refer to figure 16: power supply scheme for more details. 2.2.15 power supply supervisor the devices have an integrated power-on reset (por) / power-down reset (pdr) circuitry coupled with a brownout reset (bor) circuitr y. at power-on, bor is always active, and ensures proper operation starting from 1.8 v. after the 1.8 v bor threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable bor permanently. three bor thresholds are available through option bytes. the device remains in reset mode when v dd is below a specified threshold, v por/pdr or v bor , without the need for an external reset circuit. the devices also feature an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 2.2.16 voltage regulator the regulator has four operating modes: regulator on ? main regulator mode (mr) ? low power regulator (lpr) ? power-down regulator off ? regulator off/internal reset on
description stm32f21xxx 22/173 doc id 17050 rev 8 regulator on the regulator on modes are activated by default on lqfp packages. on ufbga176 package, they are activated by connecting regoff to v ss . v dd minimum value is 1.8 v. there are three regulator on modes: mr is used in nominal regulation mode (run) lpr is used in stop mode power-down is used in standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and sram are lost). regulator off regulator off/internal reset on on ufbga176 package, regoff must be connected to v dd . the regulator off/internal reset on mode allows to supply externally a 1.2 v voltage source through v cap_1 and v cap_2 pins, in addition to v dd . the following conditions must be respected: ?v dd should always be higher than v cap_1 and v cap_2 to avoid current injection between power domains. ? if the time for v cap_1 and v cap_2 to reach 1.08 v is faster than the time for v dd to reach 1.8 v, then pa0 should be connected to the nrst pin (see figure 6 ). otherwise, pa0 should be asserted low externally during por until v dd reaches 1.8 v (see figure 7 ). in this mode, pa0 cannot be used as a gpio pin since it allows to reset the part of the 1.2 v logic which is not reset by the nrst pin, when the internal voltage regulator in off. figure 6. startup in regulator off: slow v dd slope - power-down reset risen after v cap_1 /v cap_2 stabilization 1. this figure is valid both whatever the internal reset mode (on or off). v dd time 1.08 v 18 3 pdr=1.8 v v cap_1 /v cap_2 1.2 v time pa0 tied to nrst nrst
stm32f21xxx description doc id 17050 rev 8 23/173 figure 7. startup in regulator off: fast v dd slope - power-down reset risen before v cap_1 /v cap_2 stabilization 2.2.17 real-time clock (rtc), backup sram and backup registers the backup domain of the stm32f21x devices includes: the real-time clock (rtc) 4 kbytes of backup sram 20 backup registers the real-time clock (rtc) is an independent bcd timer/counter. dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in bcd (binary-coded decimal) format. correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. the rtc provides a programmable alarm and programmable periodic interrupts with wakeup from stop and standby modes. it is clocked by a 32.768 khz external crystal, resonator or oscillator, the internal low-power rc oscillator or the high -speed external clock divided by 128. the intern al low-speed rc has a typical frequency of 32 khz. the rtc can be calibrated using an external 512 hz output to compensate for any natural quartz deviation. two alarm registers are used to generate an alar m at a specific time and calendar fields can be independently masked for alarm comparison. to generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 s to every 36 hours. a 20-bit prescaler is used for the time base clock. it is by default configured to generate a time base of 1 second from a clock at 32.768 khz. the 4-kbyte backup sram is an eeprom-like ar ea.it can be used to store data which need to be retained in vbat and standby mode.this memory area is disabled to minimize power consumption (see section 2.2.18: low-power modes ). it can be enabled by software. the backup registers are 32-bit registers used to store 80 bytes of user application data when v dd power is not present. backup registers are not reset by a system, a power reset, or when the device wakes up from the standby mode (see section 2.2.18: low-power modes ). like backup sram, the rtc and backup registers are supplied through a switch that is powered either from the v dd supply when present or the v bat pin. v dd time 1.08 v pdr=1.8 v v cap_1 /v cap_2 1.2 v time pa0 asserted externally nrst
description stm32f21xxx 24/173 doc id 17050 rev 8 2.2.18 low-power modes the stm32f21x family supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. stop mode the stop mode achieves the lowest power consumption while retaining the contents of sram and registers. all clocks in the 1.2 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled. the voltage regulator can also be put either in normal or in low-power mode. the device can be woken up from the stop mode by any of the exti line. the exti line source can be one of the 16 external lines, the pvd output, the rtc alarm / wakeup / tamper / time stamp events, the usb otg fs/hs wakeup or the ethernet wakeup. standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.2 v domain is powered off. the pll, the hsi rc and the hse crystal oscillators are also switched off. after entering standby mode, the sram and register contents are lost except for registers in the backup domain and the backup sram when selected. the device exits the standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin, or an rtc alarm / wakeup / tamper /time stamp event occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped when the device enters the stop or standby mode. 2.2.19 v bat operation the v bat pin allows to power the device v bat domain from an external battery or an external supercapacitor. v bat operation is activated when v dd is not present. the v bat pin supplies the rtc, the backup registers and the backup sram. note: when the microcontroller is supplied from v bat , external interrupts and rtc alarm/events do not exit it from v bat operation.
stm32f21xxx description doc id 17050 rev 8 25/173 2.2.20 timers and watchdogs the stm32f21x devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. all timer counters can be frozen in debug mode. ta bl e 3 compares the features of the advanced-control, general-purpose and basic timers. advanced-control timers (tim1, tim8) the advanced-control timers (tim1, tim8) can be seen as three-phase pwm generators multiplexed on 6 channels. they have complementary pwm outputs with programmable inserted dead times. they can also be considered as complete general-purpose timers. their 4 independent channels can be used for: input capture output compare pwm generation (edge- or center-aligned modes) one-pulse mode output table 3. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary output max interface clock max timer clock advanced- control tim1, tim8 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 ye s 6 0 m h z 120 mhz general purpose tim2, tim5 32-bit up, down, up/down any integer between 1 and 65536 ye s 4 n o 3 0 m h z 60 mhz tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 n o 3 0 m h z 60 mhz basic tim6, tim7 16-bit up any integer between 1 and 65536 ye s 0 n o 3 0 m h z 60 mhz general purpose tim9 16-bit up any integer between 1 and 65536 no 2 no 60 mhz 120 mhz tim10, tim11 16-bit up any integer between 1 and 65536 no 1 no 60 mhz 120 mhz tim12 16-bit up any integer between 1 and 65536 no 2 no 30 mhz 60 mhz tim13, tim14 16-bit up any integer between 1 and 65536 no 1 no 30 mhz 60 mhz
description stm32f21xxx 26/173 doc id 17050 rev 8 if configured as standard 16-bit timers, they have the same features as the general-purpose timx timers. if configured as 16-bit pwm generators, they have full modulation capability (0- 100%). the tim1 and tim8 counters can be frozen in debug mode. many of the advanced-control timer features are shared with those of the standard timx timers which have the same architecture. the advanced-control timer can therefore work together with the timx timers via the timer link feature for synchronization or event chaining. general-purpose timers (timx) there are ten synchronizable general-purpose timers embedded in the stm32f21x devices (see ta b l e 3 for differences). tim2, tim3, tim4, tim5 the stm32f21x include 4 full-featured general-purpose timers. tim2 and tim5 are 32-bit timers, and tim3 and tim4 are 16-bit timers. the tim2 and tim5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. the tim3 and tim4 timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. they all feature 4 independent channels for input capture/output compare, pwm or one-pulse mode output. this gives up to 16 input capture/output compare/pwms on the largest packages. the tim2, tim3, tim4, tim5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers tim1 and tim8 via the timer link feature for synchr onization or event chaining. the counters of tim2, tim3, tim4, tim5 can be frozen in debug mode. any of these general-purpose timers can be used to generate pwm outputs. tim2, tim3, tim4, tim5 all have independent dma request generation. they are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. tim10, tim11 and tim9 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim10 and tim11 feature one independent channel, whereas tim9 has two independent channels for input capture/output compare, pwm or one-pulse mode output. they can be synchronized with the tim2, tim3, tim4, tim5 full-featured general-purpose timers. they can also be used as simple time bases. tim12, tim13 and tim14 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim13 and tim14 feature one independent channel, whereas tim12 has two independent channels for input capture/output compare, pwm or one-pulse mode output. they can be synchronized with the tim2, tim3, tim4, tim5 full-featured general-purpose timers. they can also be used as simple time bases. basic timers tim6 and tim7 these timers are mainly used for dac trigger and waveform generation. they can also be used as a generic 16-bit time base. independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 32 khz internal rc and as it operates independently from the
stm32f21xxx description doc id 17050 rev 8 27/173 main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. it is hardware- or software-configurable through the option bytes. the counter can be frozen in debug mode. window watchdog the window watchdog is based on a 7-bit downc ounter that can be set as free-running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrup t capability and the counter can be frozen in debug mode. systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. it features: a 24-bit downcounter autoreload capability maskable system interrupt generation when the counter reaches 0 programmable clock source 2.2.21 inter-integrated circuit interface (i2c) up to three i 2 c bus interfaces can operate in multimaster and slave modes. they can support the standard- and fast-modes. they support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). a hardware crc generation/verification is embedded. they can be served by dma and they support smbus 2.0/pmbus. 2.2.22 universal synchronous/ asynchronous receiver transmitters (uarts/usarts) the stm32f21x devices embed four universal synchronous/asynchronous receiver transmitters (usart1, usart2, usart3 and usart6) and two universal asynchronous receiver transmitters (uart4 and uart5). these six interfaces provide asynchronous communication, irda sir endec support, multiprocessor communication mode, single-wire half-duplex communication mode and have lin master/slave capability. the usar t1 and usart6 interf aces are able to communicate at speeds of up to 7.5 mbit/s. the other available interfaces communicate at up to 3.75 mbit/s. usart1, usart2, usart3 and usart6 also provide hardware management of the cts and rts signals, smart card mode (iso 7816 compliant) and spi-like communication capability. all interfaces can be served by the dma controller.
description stm32f21xxx 28/173 doc id 17050 rev 8 2.2.23 serial perip heral interface (spi) the stm32f21x devices feature up to three spis in slave and master modes in full-duplex and simplex communication modes. spi1 can communicate at up to 30 mbits/s, while spi2 and spi3 can communicate at up to 15 mbit/s. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card/mmc modes. all spis can be served by the dma controller. the spi interface can be configured to operate in ti mode for communications in master mode and slave mode. 2.2.24 inter-integrated sound (i 2 s) two standard i 2 s interfaces (multiplexed with spi2 and spi3) are available. they can operate in master or slave mode, in half-duplex communication modes, and can be configured to operate with a 16-/32-bit resolution as input or output channels. audio sampling frequencies from 8 khz up to 192 khz are supported. when either or both of the i 2 s interfaces is/are configured in master mode, the master clock can be output to the external dac/codec at 256 times the sampling frequency. all i2sx interfaces can be served by the dma controller. table 4. usart feature comparison usart name standard features modem (rts/cts) lin spi master irda smartcard (iso 7816) max. baud rate in mbit/s (oversampling by 16) max. baud rate in mbit/s (oversampling by 8) apb mapping usart1 x x x x x x 1.87 7.5 apb2 (max. 60 mhz) usart2 x x x x x x 1.87 3.75 apb1 (max. 30 mhz) usart3 x x x x x x 1.87 3.75 apb1 (max. 30 mhz) uart4 x - x - x - 1.87 3.75 apb1 (max. 30 mhz) uart5 x - x - x - 3.75 3.75 apb1 (max. 30 mhz) usart6 x x x x x x 3.75 7.5 apb2 (max. 60 mhz)
stm32f21xxx description doc id 17050 rev 8 29/173 2.2.25 sdio an sd/sdio/mmc host interface is availabl e, that supports mu ltimediacard system specification version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. the interface allows data transfer at up to 48 mhz in 8-bit mode, and is compliant with the sd memory card specification version 2.0. the sdio card specification version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. the current version supports only one sd/sdio/mmc4.2 card at any one time and a stack of mmc4.1 or previous. in addition to sd/sdio/mmc, this interface is fully compliant with the ce-ata digital protocol rev1.1. 2.2.26 ethernet mac interface with dedicated dma and ieee 1588 support peripheral available only on the stm32f217xx devices. the stm32f217xx devices provid e an ieee-802.3-2002-complia nt media access controller (mac) for ethernet lan communications through an industry-standard medium- independent interface (mii) or a reduced medium-independent interface (rmii). the stm32f217xx requires an external physical interface device (phy) to connect to the physical lan bus (twisted-pair, fiber, etc.). the phy is connected to the stm32f217xx mii port using 17 signals for mii or 9 signals for rmii, and can be clocked using the 25 mhz (mii) or 50 mhz (rmii) output from the stm32f217xx. the stm32f217xx includes the following features: supports 10 and 100 mbit/s rates dedicated dma controller allowing high-speed transfers between the dedicated sram and the descriptors (see the stm32f20x and stm32f21x reference manual for details) tagged mac frame support (vlan support) half-duplex (csma/cd) and full-duplex operation mac control sublayer (control frames) support 32-bit crc generation and removal several address filtering modes for physical and multicast address (multicast and group addresses) 32-bit status code for each transmitted or received frame internal fifos to buffer transmit and receive frames. the transmit fifo and the receive fifo are both 2 kbytes, that is 4 kbytes in total supports hardware ptp (pre cision time protocol) in accordance with ieee 1588 2008 (ptp v2) with the time stamp comparator connected to the tim2 input triggers interrupt when system time becomes greater than target time
description stm32f21xxx 30/173 doc id 17050 rev 8 2.2.27 controller area network (can) the two cans are compliant with the 2.0a and b (active) specifications with a bitrate up to 1 mbit/s. they can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. each can has three transmit mailboxes, two receive fifos with 3 stages and 28 shared scalable filter banks (all of them can be used even if one can is used). the 256 bytes of sram which are allocated for each can are not shared with any other peripheral. 2.2.28 universal se rial bus on-the-go full-speed (otg_fs) the devices embed an usb otg full-speed device/host/otg peripheral with integrated transceivers. the usb otg fs peripheral is compliant with the usb 2.0 specification and with the otg 1.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg full-speed controller requires a dedicated 48 mhz clock that is generated by a pll connected to the hse oscillato r. the major features are: combined rx and tx fifo size of 320 35 bits with dynamic fifo sizing supports the session request protocol (srp) and host negotiation protocol (hnp) 4 bidirectional endpoints 8 host channels with periodic out support hnp/snp/ip inside (no need for any external resistor) for otg/host modes, a power switch is needed in case bus-powered devices are connected internal fs otg phy support 2.2.29 universal se rial bus on-the-go high-speed (otg_hs) the stm32f21x devices embed a usb otg high-speed (up to 480 mb/s) device/host/otg peripheral. the usb otg hs supports both full-speed and high-speed operations. it integrates the transceivers for full-speed operation (12 mb/s) and features a utmi low-pin interface (ulpi) for high-speed operation (480 mb/s). when using the usb otg hs in hs mode, an external phy device connected to the ulpi is required. the usb otg hs peripheral is compliant with the usb 2.0 sp ecification and with the otg 1.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg full-speed controller requires a dedicated 48 mhz clock that is generated by a pll connected to the hse oscillato r. the major features are: combined rx and tx fifo size of 1024 35 bits with dynamic fifo sizing supports the session request protocol (srp) and host negotiation protocol (hnp) 6 bidirectional endpoints 12 host channels with periodic out support internal fs otg phy support external hs or hs otg operation supporting ulpi in sdr mode. the otg phy is connected to the microcontroller ulpi port through 12 signals. it can be clocked using the 60 mhz output. internal usb dma hnp/snp/ip inside (no need for any external resistor) for otg/host modes, a power switch is needed in case bus-powered devices are connected
stm32f21xxx description doc id 17050 rev 8 31/173 2.2.30 audio pll (plli2s) the devices feature an additional dedicated pll for audio i 2 s application. it allows to achieve error-free i 2 s sampling clock accuracy without compromising on the cpu performance, while using usb peripherals. the plli2s configuration can be modified to manage an i 2 s sample rate change without disabling the main pll (pll) used for cpu, usb and ethernet interfaces. the audio pll can be programmed with very low error to obtain sampling rates ranging from 8 khz to 192 khz. in addition to the audio pll, a master clock input pin can be used to synchronize the i2s flow with an external pll (or codec output). 2.2.31 digital came ra interface (dcmi) the camera interface is not available in stm32f215xx devices. stm32f217xx products embed a camera interface that can connect with camera modules and cmos sensors through an 8-bit to 14-bit parallel interface, to receive video data. the camera interface can sustain up to 27 mbyte/s at 27 mhz or 48 mbyte/s at 48 mhz. it features: programmable polarity for the input pixel clock and synchronization signals parallel data communication can be 8-, 10-, 12- or 14-bit supports 8-bit progressive video monochrome or raw bayer format, ycbcr 4:2:2 progressive video, rgb 565 progressive video or compressed data (like jpeg) supports continuous mode or snapshot (a single frame) mode capability to automati cally crop the image
description stm32f21xxx 32/173 doc id 17050 rev 8 2.2.32 cryptographic acceleration the stm32f215xx and stm32f217xx devices embed a cryptographic accelerator. this cryptographic accelerator provides a set of hardware acceleration for the advanced cryptographic algorithms usually needed to provide confidentiality, authentication, data integrity and non repudiation when exchanging messages with a peer. these algorithms consists of: encryption/decryption ? des/tdes (data encryption standard/triple data encryption standard): ecb (electronic codebook) and cbc (cipher bl ock chaining) chaining algorithms, 64-, 128- or 192-bit key ? aes (advanced encryption standard): ecb, cbc and ctr (counter mode) chaining algorithms, 128, 192 or 256-bit key universal hash ? sha-1 (secure hash algorithm) ?md5 it also provides a true random number generator that deliver 32-bit random numbers produced by an integrated analog circuit. 2.2.33 true random nu mber generator (rng) all stm32f2xxx products embed a true rng that delivers 32-bit random numbers produced by an integrated analog circuit.
stm32f21xxx description doc id 17050 rev 8 33/173 2.2.34 gpios (genera l-purpose inputs/outputs) each of the gpio pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (f loating, with or withou t pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. the i/o alternate function configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the i/os registers. to provide fast i/o handling, the gpios are on the fast ahb1 bus with a clock up to 120 mhz that leads to a maximum i/o toggling speed of 60 mhz. 2.2.35 adcs ( analog-to-digital converters) three 12-bit analog-to-digital converters are embedded and each adc shares up to 16 external channels, performing conversions in the single-shot or scan mode. in scan mode, automatic conversion is performed on a selected group of analog inputs. additional logic functions embedded in the adc interface allow: simultaneous sample and hold interleaved sample and hold the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. the events generated by the timers tim1, tim2, tim3, tim4, tim5 and tim8 can be internally connected to the adc start trigger an d injection trigger, res pectively, to allow the application to synchronize a/d conversion and timers. 2.2.36 dac (digital-t o-analog converter) the two 12-bit buffered dac channels can be used to convert two digital signals into two analog voltage signal outputs. the design structure is composed of integrated resistor strings and an amplifier in inverting configuration. this dual digital interface supports the following features: two dac converters: one for each output channel 8-bit or 12-bit monotonic output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual dac channel independent or simultaneous conversions dma capability for each channel external triggers for conversion input voltage reference v ref+ eight dac trigger inputs are used in the device. the dac channels are triggered through the timer update outputs that are also connected to different dma streams.
description stm32f21xxx 34/173 doc id 17050 rev 8 2.2.37 temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 1.8 and 3.6 v. the temperature sensor is internally connected to the adc1_in16 input channel which is used to convert the sensor output voltage into a digital value. as the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. if an accurate temperature reading is needed, then an external temperature sensor part should be used. 2.2.38 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jtag tms and tck pins are shared with swdio and swclk, respectively, and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. 2.2.39 embedded trace macrocell? the arm embedded trace ma crocell provides a greater visib ility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32f21x through a small number of etm pins to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using usb, ethernet, or any other high-speed channel. real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. tpa hardware is commercially available from common development tool vendors. the embedded trace macrocell operates with third party debugger software tools.
stm32f21xxx pinouts and pin description doc id 17050 rev 8 35/173 3 pinouts and pin description figure 8. stm32f21x lqfp64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vbat pc14-osc32_in pc15-osc32_out nrst pc0 pc1 pc2 pc3 vssa vdda pa0-wkup pa1 pa2 vdd_3 vss_3 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd2 pc12 pc11 pc10 pa15 pa14 vdd_2 vcap_2 pa13 pa12 pa11 pa10 pa9 pa8 pc9 pc8 pc7 pc6 pb15 pb14 pb13 pb12 pa3 vss_4 vdd_4 pa4 pa5 pa6 pa7 pc4 pc5 pb0 pb1 pb2 pb10 pb11 vcap_1 vdd_1 lqfp64 ai15969b pc13-rtc_af1 ph0-osc_in ph1-osc_out
pinouts and pin description stm32f21xxx 36/173 doc id 17050 rev 8 figure 9. stm32f21x lqfp100 pinout 1. rfu means ?reserved for future use?. this pin can be tied to v dd ,v ss or left unconnected. 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 pe2 pe3 pe4 pe5 pe6 vbat pc14-osc32_in pc15-osc32_out vss_5 vdd_5 ph0-osc_in nrst pc0 pc1 pc2 pc3 vdd_12 vssa vref+ vdda pa0-wkup pa1 pa2 vdd_2 vss_2 vcap_2 pa 13 pa 12 pa 11 pa 10 pa 9 pa 8 pc9 pc8 pc7 pc6 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pb15 pb14 pb13 pb12 pa3 vss_4 vdd_4 pa4 pa5 pa6 pa7 pc4 pc5 pb0 pb1 pb2 pe7 pe8 pe9 pe10 pe11 pe12 pe13 pe14 pe15 pb10 pb11 vcap_1 vdd_1 rfu vdd_3 pe1 pe0 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc11 pc10 pa15 pa14 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ai15970d lqfp100 pc13-rtc_af1 ph1-osc_out
stm32f21xxx pinouts and pin description doc id 17050 rev 8 37/173 figure 10. stm32f21x lqfp144 pinout 1. rfu means ?reserved for future use?. this pin can be tied to v dd ,v ss or left unconnected. rfu v dd_3 pe1 pe0 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pg15 v dd_11 v ss_11 pg14 pg13 pg12 pg11 pg10 pg9 pd7 pd6 v dd_10 v ss_10 pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc11 pc10 pa 15 pa 14 pe2 v dd_2 pe3 v ss_2 pe4 pe5 pa 13 pe6 pa 12 vbat pa 11 pc13-rtc_af1 pa 10 pc14-osc32_in pa 9 pc15-osc32_out pa 8 pf0 pc9 pf1 pc8 pf2 pc7 pf3 pc6 pf4 v dd_9 pf5 v ss_9 v ss_5 pg8 v dd_5 pg7 pf6 pg6 pf7 pg5 pf8 pg4 pf9 pg3 pf10 pg2 ph0-osc_in pd15 ph1-osc_out pd14 nrst v dd_8 pc0 v ss_8 pc1 pd13 pc2 pd12 pc3 pd11 v ssa pd10 v dd_12 pd9 v ref+ pd8 v dda pb15 pa 0-w kup pb14 pa 1 pb13 pa 2 pb12 pa 3 v ss_4 v dd_4 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pf11 pf12 vss_6 v dd_6 pf13 pf14 pf15 pg0 pg1 pe7 pe8 pe9 v ss_7 v dd_7 pe10 pe11 pe12 pe13 pe14 pe15 pb10 pb11 v cap_1 v dd_1 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 109 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 72 lqfp144 120 119 118 117 116 115 114 113 112 111 110 61 62 63 64 65 66 67 68 69 70 71 26 27 28 29 30 31 32 33 34 35 36 83 82 81 80 79 78 77 76 75 74 73 ai15971d v cap_2
pinouts and pin description stm32f21xxx 38/173 doc id 17050 rev 8 figure 11. stm32f21x lqfp176 pinout 1. rfu means ?reserved for future use?. this pin can be tied to v dd ,v ss or left unconnected. rfu v dd_3 pe1 pe0 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pg15 v dd_11 v ss_11 pg14 pg13 pg12 pg11 pg10 pg9 pd7 pd6 v dd_10 v ss_10 pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc11 pc10 pi7 pi6 pe2 v dd_2 pe3 v ss_2 pe4 pe5 pa13 pe6 pa12 vbat pa11 pi8-rtc_af2 pa10 pc14-osc32_in pa9 pc15-osc32_out pa8 pf0 pc9 pf1 pc8 pf2 pc7 pf3 pc6 pf4 v dd_9 pf5 v ss_9 v ss_5 pg8 v dd_5 pg7 pf6 pg6 pf7 pg5 pf8 pg4 pf9 pg3 pf10 pg2 ph0-osc_in pd15 ph1-osc_out pd14 nrst v dd_8 pc0 v ss_8 pc1 pd13 pc2 pd12 pc3 pd11 v ssa pd10 v dd_12 pd9 v ref+ pd8 v dda pb15 pa0-wkup pb14 pa1 pb13 pa2 pb12 pa3 v ss_4 v dd_4 pa4 pa5 pa6 pa7 pc4 pc5 pb0 pb1 pb2 pf11 pf12 vss_6 v dd_6 pf13 pf14 pf15 pg0 pg1 pe7 pe8 pe9 v ss_7 v dd_7 pe10 pe11 pe12 pe13 pe14 pe15 pb10 pb11 v cap_1 v dd_1 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 141 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 80 lqfp176 152 151 150 149 148 147 146 145 144 143 142 69 70 71 72 73 74 75 76 77 78 79 26 27 28 29 30 31 32 33 34 35 36 107 106 105 104 103 102 101 100 99 98 89 ai15972d v cap_2 pi4 pa15 pa14 v dd_15 v ss_15 pi3 pi2 pi5 140 139 138 137 136 135 134 133 ph4 ph5 ph6 ph7 ph8 ph9 ph10 ph11 88 81 82 83 84 85 86 87 pi1 pi0 ph15 ph14 ph13 v dd_14 v ss_14 ph12 96 95 94 93 92 91 90 97 37 38 39 40 41 42 43 44 pc13-rtc_af1 pi9 pi10 pi11 v ss_13 v dd_13 ph2 ph3
stm32f21xxx pinouts and pin description doc id 17050 rev 8 39/173 figure 12. stm32f21x ufbga176 ballout 1. rfu means ?reserved for future use?. this pin can be tied to v dd ,v ss or left unconnected. 2. top view. 1 2 3 9 10 11 12 13 14 15 a pe3 pe2 pe1 pe0 pb8 pb5 pg14 pg13 pb4 pb3 pd7 pc12 pa15 pa14 pa13 b pe4 pe5 pe6 pb9 pb7 pb6 pg15 pg12 pg11 pg10 pd6 pd0 pc11 pc10 pa12 cvbatpi7pi6pi5 rfu vdd_3 vdd_11 vdd_10 vdd_15 pg9 pd5 pd1 pi3 pi2 pa11 d pc13- tamp1 pi8- tamp2 pi9 pi4 boot0 vss_11 vss_10 vss_15 pd4 pd3 pd2 ph15 pi1 pa10 e pc14- osc32_in pf0 pi10 pi11 ph13 ph14 pi0 pa9 f pc15- osc32_out vss_13 vdd_13 ph2 vss vss vss vss vss vss_2 vcap2 pc9 pa8 g ph0- osc_in vss_5 vdd_5 ph3 vss vss vss vss vss vss_9 vdd_2 pc8 pc7 h ph1- osc_out pf2 pf1 ph4 vss vss vss vss vss vss_14 vdd_9 pg8 pc6 j nrst pf3 pf4 ph5 vss vss vss vss vss vdd_14 vdd_8 pg7 pg6 k pf7 pf6 pf5 vdd_4 vss vss vss vss vss ph12 pg5 pg4 pg3 l pf10 pf9 pf8 regoff ph11 ph10 pd15 pg2 m vssa pc0 pc1 pc2 pc3 pb2 pg1 vss_6 vss_7 vcap1 ph6 ph8 ph9 pd14 pd13 nvref-pa1 pa0- wkup pa4 pc4 pf13 pg0 vdd_6 vdd_7 vdd_1 pe13 ph7 pd12 pd11 pd10 p vref+ pa2 pa6 pa5 pc5 pf12 pf15 pe8 pe9 pe11 pe14 pb12 pb13 pd9 pd8 r vdda pa3 pa7 pb1 pb0 pf11 pf14 pe7 pe10 pe12 pe15 pb10 pb11 pb14 pb15 ai17293b vss 4 35678 table 5. stm32f21x pin and ball definitions pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions other functions lqfp64 lqfp100 lqfp144 lqfp176 ufbga176 - 1 1 1 a2 pe2 i/o ft pe2 traceclk/ fsmc_a23 / eth_mii_txd3 / eventout - 2 2 2 a1 pe3 i/o ft pe3 traced0/fsmc_a19/ eventout - 3 3 3 b1 pe4 i/o ft pe4 traced1/fsmc_a20 / dcmi_d4/ eventout - 4 4 4 b2 pe5 i/o ft pe5 traced2 / fsmc_a21 / tim9_ch1 / dcmi_d6/ eventout - 5 5 5 b3 pe6 i/o ft pe6 traced3 / fsmc_a22 / tim9_ch2 / dcmi_d7/ eventout 1666c1 v bat sv bat
pinouts and pin description stm32f21xxx 40/173 doc id 17050 rev 8 ---7d2 pi8 (4) i/o ft pi8 (5) eventout rtc_af2 2778d1 pc13 (4) i/o ft pc13 (5) eventout rtc_af1 3889e1pc14 (4) -osc32_in (6) i/o ft pc14 (5) eventout osc32_in 49910f1 pc15 (4) - osc32_out (6) i/o ft pc15 (5) eventout osc32_out - - - 11 d3 pi9 i/o ft pi9 can1_rx / eventout ---12e3 pi10 i/oft pi10 eth_mii_rx_er/ eventout ---13e4 pi11 i/oft pi11 otg_hs_ulpi_dir/ eventout ---14f2 v ss_13 sv ss_13 ---15f3 v dd_13 sv dd_13 - - 10 16 e2 pf0 i/o ft pf0 fsmc_a0 / i2c2_sda/ eventout - - 11 17 h3 pf1 i/o ft pf1 fsmc_a1 / i2c2_scl/ eventout - - 12 18 h2 pf2 i/o ft pf2 fsmc_a2 / i2c2_smba/ eventout - - 13 19 j2 pf3 (6) i/o ft pf3 fsmc_a3/ eventout adc3_in9 - - 14 20 j3 pf4 (6) i/o ft pf4 fsmc_a4/ eventout adc3_in14 --1521k3 pf5 (6) i/o ft pf5 fsmc_a5/ eventout adc3_in15 -101622g2 v ss_5 sv ss_5 -111723g3 v dd_5 sv dd_5 --1824k2 pf6 (6) i/o ft pf6 tim10_ch1 / fsmc_niord/ eventout adc3_in4 --1925k1 pf7 (6) i/o ft pf7 tim11_ch1/fsmc_nreg/ eventout adc3_in5 - - 20 26 l3 pf8 (6) i/o ft pf8 tim13_ch1 / fsmc_niowr/ eventout adc3_in6 - - 21 27 l2 pf9 (6) i/o ft pf9 tim14_ch1 / fsmc_cd/ eventout adc3_in7 - - 22 28 l1 pf10 (6) i/o ft pf10 fsmc_intr/ eventout adc3_in8 5122329g1 ph0 (6) -osc_in i/o ft ph0 eventout osc_in 6132430h1 ph1 (6) -osc_out i/o ft ph1 eventout osc_out 7 14 25 31 j1 nrst i/o nrst table 5. stm32f21x pin and ball definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions other functions lqfp64 lqfp100 lqfp144 lqfp176 ufbga176
stm32f21xxx pinouts and pin description doc id 17050 rev 8 41/173 8152632m2 pc0 (6) i/o ft pc0 otg_hs_ulpi_stp/ eventout adc123_ in10 9162733m3 pc1 (6) i/o ft pc1 eth_mdc/ eventout adc123_ in11 10 17 28 34 m4 pc2 (6) i/o ft pc2 spi2_miso / otg_hs_ulpi_dir / eth_mii_txd2/ eventout adc123_ in12 11 18 29 35 m5 pc3 (6) i/o ft pc3 spi2_mosi / i2s2_sd / otg_hs_ulpi_nxt / eth_mii_tx_clk/ eventout adc123_ in13 -193036 - v dd_12 sv dd_12 12 20 31 37 m1 v ssa sv ssa ----n1 v ref- sv ref- -213238p1 v ref+ sv ref+ 13 22 33 39 r1 v dda sv dda 14 23 34 40 n3 pa0 (7) -wkup (6) i/o ft pa0-wkup usart2_cts/ uart4_tx/ eth_mii_crs / tim2_ch1_etr/ tim5_ch1 / tim8_etr/ eventout adc123_in0/ wkup 15 24 35 41 n2 pa1 (6) i/o ft pa1 usart2_rts / uart4_rx/ eth_rmii_ref_clk / eth_mii_rx_clk / tim5_ch2 / tim2_ch2/ eventout adc123_in1 16 25 36 42 p2 pa2 (6) i/o ft pa2 usart2_tx/tim5_ch3 / tim9_ch1 / tim2_ch3 / eth_mdio/ eventout adc123_in2 - - - 43 f4 ph2 i/o ft ph2 eth_mii_crs/ eventout - - - 44 g4 ph3 i/o ft ph3 eth_mii_col/ eventout ---45h4 ph4 i/oft ph4 i2c2_scl / otg_hs_ulpi_nxt/ eventout - - - 46 j4 ph5 i/o ft ph5 i2c2_sda/ eventout 17 26 37 47 r2 pa3 (6) i/o ft pa3 usart2_rx/tim5_ch4 / tim9_ch2 / tim2_ch4 / otg_hs_ulpi_d0 / eth_mii_col/ eventout adc123_in3 table 5. stm32f21x pin and ball definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions other functions lqfp64 lqfp100 lqfp144 lqfp176 ufbga176
pinouts and pin description stm32f21xxx 42/173 doc id 17050 rev 8 18 27 38 48 - v ss_4 sv ss_4 l4 regoff i/o regoff 19 28 39 49 k4 v dd_4 sv dd_4 20 29 40 50 n4 pa4 (6) i/o tt pa4 spi1_nss / spi3_nss / usart2_ck / dcmi_hsync / otg_hs_sof/ i2s3_ws/ eventout adc12_in4 /dac_out1 21 30 41 51 p4 pa5 (6) i/o tt pa5 spi1_sck/ otg_hs_ulpi_ck / tim2_ch1_etr/ tim8_ch1n/ eventout adc12_in5 /dac_out2 22 31 42 52 p3 pa6 (6) i/o ft pa6 spi1_miso / tim8_bkin/tim13_ch1 / dcmi_pixclk / tim3_ch1 / tim1_bkin/ eventout adc12_in6 23 32 43 53 r3 pa7 (6) i/o ft pa7 spi1_mosi/ ti m8_ch1n / tim14_ch1 tim3_ch2/ eth_mii_rx_dv / tim1_ch1n / eth_rmii_crs_dv/ eventout adc12_in7 24 33 44 54 n5 pc4 (6) i/o ft pc4 eth_rmii_rx_d0 / eth_mii_rx_d0/ eventout adc12_in14 25 34 45 55 p5 pc5 (6) i/o ft pc5 eth_rmii_rx_d1 / eth_mii_rx_d1 / eventout adc12_in15 26 35 46 56 r5 pb0 (6) i/o ft pb0 tim3_ch3 / tim8_ch2n/ otg_hs_ulpi_d1/ eth_mii_rxd2 / tim1_ch2n/ eventout adc12_in8 27 36 47 57 r4 pb1 (6) i/o ft pb1 tim3_ch4 / tim8_ch3n/ otg_hs_ulpi_d2/ eth_mii_rxd3 / tim1_ch3n/ eventout adc12_in9 28 37 48 58 m6 pb2 i/o ft pb2-boot1 eventout - - 49 59 r6 pf11 i/o ft pf11 dcmi_12/ eventout - - 50 60 p6 pf12 i/o ft pf12 fsmc_a6/ eventout --5161m8 v ss_6 sv ss_6 table 5. stm32f21x pin and ball definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions other functions lqfp64 lqfp100 lqfp144 lqfp176 ufbga176
stm32f21xxx pinouts and pin description doc id 17050 rev 8 43/173 --5262n8 v dd_6 sv dd_6 - - 53 63 n6 pf13 i/o ft pf13 fsmc_a7/ eventout - - 54 64 r7 pf14 i/o ft pf14 fsmc_a8/ eventout - - 55 65 p7 pf15 i/o ft pf15 fsmc_a9/ eventout - - 56 66 n7 pg0 i/o ft pg0 fsmc_a10/ eventout - - 57 67 m7 pg1 i/o ft pg1 fsmc_a11/ eventout - 38 58 68 r8 pe7 i/o ft pe7 fsmc_d4/tim1_etr/ eventout - 39 59 69 p8 pe8 i/o ft pe8 fsmc_d5/tim1_ch1n/ eventout - 40 60 70 p9 pe9 i/o ft pe9 fsmc_d6/tim1_ch1/ eventout --6171m9 v ss_7 sv ss_7 --6272n9 v dd_7 sv dd_7 - 41 63 73 r9 pe10 i/o ft pe10 fsmc_d7/tim1_ch2n/ eventout - 42 64 74 p10 pe11 i/o ft pe11 fsmc_d8/tim1_ch2/ eventout - 43 65 75 r10 pe12 i/o ft pe12 fsmc_d9/tim1_ch3n/ eventout - 44 66 76 n11 pe13 i/o ft pe13 fsmc_d10/tim1_ch3/ eventout - 45 67 77 p11 pe14 i/o ft pe14 fsmc_d11/tim1_ch4/ eventout - 46 68 78 r11 pe15 i/o ft pe15 fsmc_d12/tim1_bkin/ eventout 29 47 69 79 r12 pb10 i/o ft pb10 spi2_sck/ i2s2_sck/ i2c2_scl / usart3_tx / otg_hs_ulpi_d3 / eth_mii_rx_er / tim2_ch3/ eventout 30 48 70 80 r13 pb11 i/o ft pb11 i2c2_sda/usart3_rx/ otg_hs_ulpi_d4 / eth_rmii_tx_en/ eth_mii_tx_en / tim2_ch4/ eventout 31 49 71 81 m10 v cap_1 sv cap_1 32 50 72 82 n10 v dd_1 sv dd_1 table 5. stm32f21x pin and ball definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions other functions lqfp64 lqfp100 lqfp144 lqfp176 ufbga176
pinouts and pin description stm32f21xxx 44/173 doc id 17050 rev 8 ---83m11 ph6 i/oft ph6 i2c2_smba / tim12_ch1 / eth_mii_rxd2/ eventout ---84n12 ph7 i/oft ph7 i2c3_scl / eth_mii_rxd3/ eventout ---85m12 ph8 i/oft ph8 i2c3_sda / dcmi_hsync/ eventout ---86m13 ph9 i/oft ph9 i2c3_smba / tim12_ch2/ dcmi_d0/ eventout - - - 87 l13 ph10 i/o ft ph10 tim5_ch1 / dcmi_d1/ eventout - - - 88 l12 ph11 i/o ft ph11 tim5_ch2 / dcmi_d2/ eventout ---89k12 ph12 i/oft ph12 tim5_ch3 / dcmi_d3/ eventout ---90h12 v ss_14 sv ss_14 ---91j12 v dd_14 sv dd_14 33 51 73 92 p12 pb12 i/o ft pb12 spi2_nss/i2s2_ws/ i2c2_smba/ usart3_ck/ tim1_bkin / can2_rx / otg_hs_ulpi_d5/ eth_rmii_txd0 / eth_mii_txd0/ otg_hs_id/ eventout 34 52 74 93 p13 pb13 i/o ft pb13 spi2_sck / i2s2_sck / usart3_cts/ tim1_ch1n /can2_tx / otg_hs_ulpi_d6 / eth_rmii_txd1 / eth_mii_txd1/ eventout otg_hs_ vbus 35 53 75 94 r14 pb14 i/o ft pb14 spi2_miso/ ti m1_ch2n / tim12_ch1 / otg_hs_dm usart3_rts/ tim8_ch2n/ eventout 36 54 76 95 r15 pb15 i/o ft pb15 spi2_mosi / i2s2_sd / tim1_ch3n / tim8_ch3n / tim12_ch2 / otg_hs_dp / rtc_50hz / eventout -557796p15 pd8 i/oft pd8 fsmc_d13 / usart3_tx/ eventout table 5. stm32f21x pin and ball definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions other functions lqfp64 lqfp100 lqfp144 lqfp176 ufbga176
stm32f21xxx pinouts and pin description doc id 17050 rev 8 45/173 -567897p14 pd9 i/oft pd9 fsmc_d14 / usart3_rx/ eventout -577998n15 pd10 i/oft pd10 fsmc_d15 / usart3_ck/ eventout -588099n14 pd11 i/oft pd11 fsmc_a16/usart3_cts/ eventout - 59 81 100 n13 pd12 i/o ft pd12 fsmc_a17/tim4_ch1 / usart3_rts/ eventout - 60 82 101 m15 pd13 i/o ft pd13 fsmc_a18/tim4_ch2/ eventout - - 83 102 - v ss_8 sv ss_8 - - 84 103 j13 v dd_8 sv dd_8 - 61 85 104 m14 pd14 i/o ft pd14 fsmc_d0/tim4_ch3/ eventout - 62 86 105 l14 pd15 i/o ft pd15 fsmc_d1/tim4_ch4/ eventout - - 87 106 l15 pg2 i/o ft pg2 fsmc_a12/ eventout - - 88 107 k15 pg3 i/o ft pg3 fsmc_a13/ eventout - - 89 108 k14 pg4 i/o ft pg4 fsmc_a14/ eventout - - 90 109 k13 pg5 i/o ft pg5 fsmc_a15/ eventout - - 91 110 j15 pg6 i/o ft pg6 fsmc_int2/ eventout - - 92 111 j14 pg7 i/o ft pg7 fsmc_int3 /usart6_ck/ eventout - - 93 112 h14 pg8 i/o ft pg8 usart6_rts / eth_pps_out/ eventout - - 94 113 g12 v ss_9 sv ss_9 - - 95 114 h13 v dd_9 sv dd_9 37 63 96 115 h15 pc6 i/o ft pc6 i2s2_mck / tim8_ch1/sdio_d6 / usart6_tx / dcmi_d0/tim3_ch1/ eventout 38 64 97 116 g15 pc7 i/o ft pc7 i2s3_mck / tim8_ch2/sdio_d7 / usart6_rx / dcmi_d1/tim3_ch2/ eventout table 5. stm32f21x pin and ball definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions other functions lqfp64 lqfp100 lqfp144 lqfp176 ufbga176
pinouts and pin description stm32f21xxx 46/173 doc id 17050 rev 8 39 65 98 117 g14 pc8 i/o ft pc8 tim8_ch3/sdio_d0 /tim3_ch3/ usart6_ck / dcmi_d2/ eventout 40 66 99 118 f14 pc9 i/o ft pc9 i2s2_ckin/ i2s3_ckin/ mco2 / tim8_ch4/sdio_d1 / /i2c3_sda / dcmi_d3 / tim3_ch4/ eventout 41 67 100 119 f15 pa8 i/o ft pa8 mco1 / usart1_ck/ tim1_ch1/ i2c3_scl/ otg_fs_sof/ eventout 42 68 101 120 e15 pa9 i/o ft pa9 usart1_tx/ tim1_ch2 / i2c3_smba / dcmi_d0/ eventout otg_fs_ vbus 43 69 102 121 d15 pa10 i/o ft pa10 usart1_rx/ tim1_ch3/ otg_fs_id/dcmi_d1/ eventout 44 70 103 122 c15 pa11 i/o ft pa11 usart1_cts / can1_rx / tim1_ch4 / otg_fs_dm/ eventout 45 71 104 123 b15 pa12 i/o ft pa12 usart1_rts / can1_tx/ tim1_etr/ otg_fs_dp/ eventout 46 72 105 124 a15 pa13 i/o ft jtms-swdio jtms-swdio/ eventout 47 73 106 125 f13 v cap_2 sv cap_2 - 74 107 126 f12 v ss_2 sv ss_2 48 75 108 127 g13 v dd_2 sv dd_2 - - - 128 e12 ph13 i/o ft ph13 tim8_ch1n / can1_tx/ eventout - - - 129 e13 ph14 i/o ft ph14 tim8_ch2n / dcmi_d4/ eventout - - - 130 d13 ph15 i/o ft ph15 tim8_ch3n / dcmi_d11/ eventout - - - 131 e14 pi0 i/o ft pi0 tim5_ch4 / spi2_nss / i2s2_ws / dcmi_d13/ eventout - - - 132 d14 pi1 i/o ft pi1 spi2_sck / i2s2_sck / dcmi_d8/ eventout - - - 133 c14 pi2 i/o ft pi2 tim8_ch4 /spi2_miso / dcmi_d9/ eventout table 5. stm32f21x pin and ball definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions other functions lqfp64 lqfp100 lqfp144 lqfp176 ufbga176
stm32f21xxx pinouts and pin description doc id 17050 rev 8 47/173 - - - 134 c13 pi3 i/o ft pi3 tim8_etr / spi2_mosi / i2s2_sd / dcmi_d10/ eventout - - - 135 d9 v ss_15 sv ss_15 - - - 136 c9 v dd_15 sv dd_15 49 76 109 137 a14 pa14 i/o ft jtck -swclk jtck-swclk/ eventout 50 77 110 138 a13 pa15 i/o ft jtdi jtdi/ spi3_nss/ i2s3_ws/tim2_ch1_etr / spi1_nss/ eventout 51 78 111 139 b14 pc10 i/o ft pc10 spi3_sck / i2s3_sck / uart4_tx / sdio_d2 / dcmi_d8 / usart3_tx/ eventout 52 79 112 140 b13 pc11 i/o ft pc11 uart4_rx/ spi3_miso / sdio_d3 / dcmi_d4/usart3_rx/ eventout 53 80 113 141 a12 pc12 i/o ft pc12 uart5_tx/sdio_ck / dcmi_d9 / spi3_mosi / i2s3_sd / usart3_ck/ eventout - 81 114 142 b12 pd0 i/o ft pd0 fsmc_d2/can1_rx/ eventout - 82 115 143 c12 pd1 i/o ft pd1 fsmc_d3 / can1_tx/ eventout 54 83 116 144 d12 pd2 i/o ft pd2 tim3_etr/uart5_rx sdio_cmd / dcmi_d11/ eventout - 84 117 145 d11 pd3 i/o ft pd3 fsmc_clk/usart2_cts/ eventout - 85 118 146 d10 pd4 i/o ft pd4 fsmc_noe/usart2_rts/ eventout - 86 119 147 c11 pd5 i/o ft pd5 fsmc_nwe/usart2_tx/ eventout - - 120 148 d8 v ss_10 sv ss_10 - - 121 149 c8 v dd_10 sv dd_10 - 87 122 150 b11 pd6 i/o ft pd6 fsmc_nwait/usart2_rx / eventout - 88 123 151 a11 pd7 i/o ft pd7 usart2_ck/fsmc_ne1/f smc_nce2/ eventout table 5. stm32f21x pin and ball definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions other functions lqfp64 lqfp100 lqfp144 lqfp176 ufbga176
pinouts and pin description stm32f21xxx 48/173 doc id 17050 rev 8 - - 124 152 c10 pg9 i/o ft pg9 usart6_rx / fsmc_ne2/fsmc_nce3/ eventout - - 125 153 b10 pg10 i/o ft pg10 fsmc_nce4_1/ fsmc_ne3/ eventout - - 126 154 b9 pg11 i/o ft pg11 fsmc_nce4_2 / eth_mii_tx_en / eth _rmii_tx_en/ eventout - - 127 155 b8 pg12 i/o ft pg12 fsmc_ne4 / usart6_rts/ eventout - - 128 156 a8 pg13 i/o ft pg13 fsmc_a24 / usart6_cts /eth_mii_txd0/ eth_rmii_txd0/ eventout - - 129 157 a7 pg14 i/o ft pg14 fsmc_a25 / usart6_tx /eth_mii_txd1/ eth_rmii_txd1/ eventout - - 130 158 d7 v ss_11 sv ss_11 - - 131 159 c7 v dd_11 sv dd_11 - - 132 160 b7 pg15 i/o ft pg15 usart6_cts / dcmi_d13/ eventout 55 89 133 161 a10 pb3 i/o ft jtdo/ traceswo jtdo/ traceswo/ spi3_sck / i2s3_sck / tim2_ch2 / spi1_sck/ eventout 56 90 134 162 a9 pb4 i/o ft njtrst njtrst/ spi3_miso / tim3_ch1 / spi1_miso/ eventout 57 91 135 163 a6 pb5 i/o ft pb5 i2c1_smba/ can2_rx / otg_hs_ulpi_d7 / eth_pps_out/tim3_ch2 / spi1_mosi/ spi3_mosi / dcmi_d10 / i2s3_sd/ eventout 58 92 136 164 b6 pb6 i/o ft pb6 i2c1_scl/ tim4_ch1 / can2_tx / dcmi_d5/usart1_tx/ eventout table 5. stm32f21x pin and ball definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions other functions lqfp64 lqfp100 lqfp144 lqfp176 ufbga176
stm32f21xxx pinouts and pin description doc id 17050 rev 8 49/173 59 93 137 165 b5 pb7 i/o ft pb7 i2c1_sda / fsmc_nl (8) / dcmi_vsync / usart1_rx/ tim4_ch2/ eventout 60 94 138 166 d6 boot0 i boot0 v pp 61 95 139 167 a5 pb8 i/o ft pb8 tim4_ch3/sdio_d4/ tim10_ch1 / dcmi_d6 / eth_mii_txd3 / i2c1_scl/ can1_rx/ eventout 62 96 140 168 b4 pb9 i/o ft pb9 spi2_nss/ i2s2_ws / tim4_ch4/ tim11_ch1/ sdio_d5 / dcmi_d7 / i2c1_sda / can1_tx/ eventout - 97 141 169 a4 pe0 i/o ft pe0 tim4_etr / fsmc_nbl0 / dcmi_d2/ eventout - 98 142 170 a3 pe1 i/o ft pe1 fsmc_nbl1 / dcmi_d3/ eventout ----d5 v ss sv ss 63 - - - - v ss_3 sv ss_3 - 99 143 171 c6 rfu (9) 64 100 144 172 c5 v dd_3 sv dd_3 - - - 173 d4 pi4 i/o ft pi4 tim8_bkin / dcmi_d5/ eventout - - - 174 c4 pi5 i/o ft pi5 tim8_ch1 / dcmi_vsync/ eventout - - - 175 c3 pi6 i/o ft pi6 tim8_ch2 / dcmi_d6/ eventout - - - 176 c2 pi7 i/o ft pi7 tim8_ch3 / dcmi_d7/ eventout 1. i = input, o = output, s = supply, hiz = high impedance. 2. ft = 5 v tolerant; tt = 3.6 v tolerant. 3. function availability depends on the chosen device. 4. pc13, pc14, pc15 and pi8 are supplied through the power switch . since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 and pi8 in output mode is limited: the speed should not exceed 2 mhz with a maximum load of 30 pf and these i/os must not be us ed as a current source (e.g. to drive an led). 5. main function after the first backup domain power-up. later on, it depends on the contents of the rtc registers even after reset (because these registers are not reset by the main rese t). for details on how to manage these i/os, refer to the rtc register description sections in the stm32f20x and stm32f21x reference manual, available from t he stmicroelectronics website: www.st.com. 6. ft = 5 v tolerant except when in analog mode or oscillator mode (for pc 14, pc15, ph0 and ph1). table 5. stm32f21x pin and ball definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions other functions lqfp64 lqfp100 lqfp144 lqfp176 ufbga176
pinouts and pin description stm32f21xxx 50/173 doc id 17050 rev 8 7. if the device is delivered in an ufbga176 pac kage and if the regoff pin is set to v dd (regulator off), then pa0 is used as an internal reset (active low). 8. fsmc_nl pin is also named fsmc_nadv on memory devices. 9. rfu means ?reserved for future use?. this pin can be tied to v dd ,v ss or left unconnected. table 6. fsmc pin definition pins fsmc lqfp100 cf nor/psram/s ram nor/psram mux nand 16 bit pe2 a23 a23 yes pe3 a19 a19 yes pe4 a20 a20 yes pe5 a21 a21 yes pe6 a22 a22 yes pf0 a0 a0 - pf1 a1 a1 - pf2 a2 a2 - pf3 a3 a3 - pf4 a4 a4 - pf5 a5 a5 - pf6 niord - pf7 nreg - pf8 niowr - pf9 cd - pf10 intr - pf12 a6 a6 - pf13 a7 a7 - pf14 a8 a8 - pf15 a9 a9 - pg0 a10 a10 - pg1 a11 - pe7 d4 d4 da4 d4 yes pe8 d5 d5 da5 d5 yes pe9 d6 d6 da6 d6 yes pe10 d7 d7 da7 d7 yes pe11 d8 d8 da8 d8 yes pe12 d9 d9 da9 d9 yes pe13 d10 d10 da10 d10 yes
stm32f21xxx pinouts and pin description doc id 17050 rev 8 51/173 pe14 d11 d11 da11 d11 yes pe15 d12 d12 da12 d12 yes pd8 d13 d13 da13 d13 yes pd9 d14 d14 da14 d14 yes pd10 d15 d15 da15 d15 yes pd11 a16 a16 cle yes pd12 a17 a17 ale yes pd13 a18 a18 yes pd14 d0 d0 da0 d0 yes pd15 d1 d1 da1 d1 yes pg2 a12 - pg3 a13 - pg4 a14 - pg5 a15 - pg6 int2 - pg7 int3 - pd0 d2 d2 da2 d2 yes pd1 d3 d3 da3 d3 yes pd3 clk clk yes pd4 noe noe noe noe yes pd5 nwe nwe nwe nwe yes pd6 nwait nwait nwait nwait yes pd7 ne1 ne1 nce2 yes pg9 ne2 ne2 nce3 - pg10 nce4_1 ne3 ne3 - pg11 nce4_2 - pg12 ne4 ne4 - pg13 a24 a24 - pg14 a25 a25 - pb7 nadv nadv yes pe0 nbl0 nbl0 yes pe1 nbl1 nbl1 yes table 6. fsmc pin definition (continued) pins fsmc lqfp100 cf nor/psram/s ram nor/psram mux nand 16 bit
pinouts and pin description stm32f21xxx 52/173 doc id 17050 rev 8 table 7. alternate function mapping port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/i2c2/i2c3 spi1/spi2/i2s2 spi3/i2s3 usart1/2/3 uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_hs dcmi pa0-wkup tim2_ch1_etr tim 5_ch1 tim8_etr usart2_cts uart4_tx eth_mii_crs eventout pa1 tim2_ch2 tim5_ch2 usart2_rts uart4_rx eth_mii _rx_clk eth_rmii _ref_clk eventout pa2 tim2_ch3 tim5_ch3 tim9_ch1 usart2_tx eth_mdio eventout pa3 tim2_ch4 tim5_ch4 tim9_ch2 usart2_r x otg_hs_ulpi_d0 eth _mii_col eventout pa 4 spi1_nss spi3_nss i2s3_ws usart2_ck otg_hs_sof dcmi_hsync eventout pa5 tim2_ch1_etr tim8_ch1n spi1_sck otg_hs_ulpi_ck eventout pa6 tim1_bkin tim3_ch1 tim8_bkin spi1_miso tim13_ch1 dcmi_pixck eventout pa7 tim1_ch1n tim3_ch2 tim8_ch1n spi1_mosi tim14_ch1 eth_mii _rx_dv eth_rmii _crs_dv eventout pa8 mco1 tim1_ch1 i2c3_scl usart1_ck otg_fs_sof eventout pa9 tim1_ch2 i2c3_smba usart1_tx dcmi_d0 eventout pa10 tim1_ch3 usart1_rx otg_fs_id dcmi_d1 eventout pa11 tim1_ch4 usart1_cts can1_rx otg_fs_dm eventout pa12 tim1_etr usart1_rts can1_tx otg_fs_dp eventout pa 1 3 j t m s - s w d i o eventout pa 1 4 j t c k - s w c l k eventout pa 1 5 j t d i tim 2_ch1 tim 2_etr spi1_nss spi3_nss i2s3_ws eventout pb0 tim1_ch2n tim3_ch3 tim8_ch2n otg_hs_ulpi_d1 eth _mii_rxd2 eventout pb1 tim1_ch3n tim3_ch4 tim8_ch3n otg_hs_ulpi_d2 eth _mii_rxd3 eventout pb2 eventout pb3 jtdo/ traceswo tim2_ch2 spi1_sck spi3_sck i2s3_sck eventout pb4 jtrst tim3_ch1 spi1_miso spi3_miso eventout pb5 tim3_ch2 i2c1_smba spi1_mosi spi3_mosi i2s3_sd can2_rx otg_hs_ulpi_d7 eth _pps_out dcmi_d10 eventout pb6 tim4_ch1 i2c1_scl usart1_tx can2_tx dcmi_d5 eventout pb7 tim4_ch2 i2c1_sda usart1_rx fsmc_nl dcmi_vsync eventout pb8 tim4_ch3 tim10_ch1 i2c1_scl can1_rx eth _mii_txd3 sdio_d4 dcmi_d6 eventout pb9 tim4_ch4 tim11_ch1 i2c1_sda spi2_nss i2s2_ws can1_tx sdio_d5 dcmi_d7 eventout pb10 tim2_ch3 i2c2_scl spi2_sck i2s2_sck usart3_tx otg_hs_ulpi_d3 eth_ mii_rx_er eventout pb11 tim2_ch4 i2c2_sda usart3_rx otg_hs_ulpi_d4 eth _mii_tx_en eth _rmii_tx_en eventout pb12 tim1_bkin i2c2_smba spi2_nss i2s2_ws usart3_ck can2_rx otg_hs_ulpi_d5 eth _mii_txd0 eth _rmii_txd0 otg_hs_id eventout pb13 tim1_ch1n spi2_sck i2s2_sck usart3_cts can2_tx otg_hs_ulpi_d6 eth _mii_txd1 eth _rmii_txd1 eventout
stm32f21xxx pinouts and pin description doc id 17050 rev 8 53/173 pb14 tim1_ch2n tim8_ch2n spi2_miso usart3_rts tim12_ch1 otg_hs_dm eventout pb15 rtc_50hz tim1_ch3n tim8_ch3n spi2_mosi i2s2_sd tim12_ch2 otg_hs_dp eventout pc0 otg_hs_ulpi_stp eventout pc1 eth_mdc eventout pc2 spi2_miso otg_hs_ulpi_dir eth _mii_txd2 eventout pc3 spi2_mosi otg_hs_ulpi_nxt eth _mii_tx_clk eventout pc4 eth_mii_rxd0 eth_rmii_rxd0 eventout pc5 eth _mii_rxd1 eth _rmii_rxd1 eventout pc6 tim3_ch1 tim8_ch1 i2s2_mck usart6_tx sdio_d6 dcmi_d0 eventout pc7 tim3_ch2 tim8_ch2 i2s3_mck usart6_rx sdio_d7 dcmi_d1 eventout pc8 tim3_ch3 tim8_ch3 usart6_ck sdio_d0 dcmi_d2 eventout pc9 mco2 tim3_ch4 tim8_ch4 i2c3_sda i2s2_ckin i2s3_ckin sdio_d1 dcmi_d3 eventout pc10 spi3_sck i2s3_sck usart3_tx uart4_tx sdio_d2 dcmi_d8 eventout pc11 spi3_miso usart3_rx uart4_rx sdio_d3 dcmi_d4 eventout pc12 spi3_mosi i2s3_sd usart3_ck uart5_tx sdio_ck dcmi_d9 eventout pc13 pc14-osc32_in pc15-osc32_out pd0 can1_rx fsmc_d2 eventout pd1 can1_tx fsmc_d3 eventout pd2 tim3_etr uart5_rx sdio_cmd dcmi_d11 eventout pd3 usart2_cts fsmc_clk eventout pd4 usart2_rts fsmc_noe eventout pd5 usart2_tx fsmc_nwe eventout pd6 usart2_rx fsmc_nwait eventout pd7 usart2_ck fsmc_ne1/ fsmc_nce2 eventout pd8 usart3_tx fsmc_d13 eventout pd9 usart3_rx fsmc_d14 eventout pd10 usart3_ck fsmc_d15 eventout pd11 usart3_cts fsmc_a16 eventout pd12 tim4_ch1 usart3_rts fsmc_a17 eventout pd13 tim4_ch2 fsmc_a18 eventout table 7. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/i2c2/i2c3 spi1/spi2/i2s2 spi3/i2s3 usart1/2/3 uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_hs dcmi
pinouts and pin description stm32f21xxx 54/173 doc id 17050 rev 8 pd14 tim4_ch3 fsmc_d0 eventout pd15 tim4_ch4 fsmc_d1 eventout pe0 tim4_etr fsmc_nbl0 dcmi_d2 eventout pe1 fsmc_bln1 dcmi_d3 eventout pe2 traceclk eth _mii_txd3 fsmc_a23 eventout pe3 traced0 fsmc_a19 eventout pe4 traced1 fsmc_a20 dcmi_d4 eventout pe5 traced2 tim9_ch1 fsmc_a21 dcmi_d6 eventout pe6 traced3 tim9_ch2 fsmc_a22 dcmi_d7 eventout pe7 tim1_etr fsmc_d4 eventout pe8 tim1_ch1n fsmc_d5 eventout pe9 tim1_ch1 fsmc_d6 eventout pe10 tim1_ch2n fsmc_d7 eventout pe11 tim1_ch2 fsmc_d8 eventout pe12 tim1_ch3n fsmc_d9 eventout pe13 tim1_ch3 fsmc_d10 eventout pe14 tim1_ch4 fsmc_d11 eventout pe15 tim1_bkin fsmc_d12 eventout pf0 i2c2_sda fsmc_a0 eventout pf1 i2c2_scl fsmc_a1 eventout pf2 i2c2_smba fsmc_a2 eventout pf3 fsmc_a3 eventout pf4 fsmc_a4 eventout pf5 fsmc_a5 eventout pf6 tim10_ch1 fsmc_niord eventout pf7 tim11_ch1 fsmc_nreg eventout pf8 tim13_ch1 fsmc_niowr eventout pf9 tim14_ch1 fsmc_cd eventout pf10 fsmc_intr eventout pf11 dcmi_d12 eventout pf12 fsmc_a6 eventout pf13 fsmc_a7 eventout pf14 fsmc_a8 eventout table 7. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/i2c2/i2c3 spi1/spi2/i2s2 spi3/i2s3 usart1/2/3 uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_hs dcmi
stm32f21xxx pinouts and pin description doc id 17050 rev 8 55/173 pf15 fsmc_a9 eventout pg0 fsmc_a10 eventout pg1 fsmc_a11 eventout pg2 fsmc_a12 eventout pg3 fsmc_a13 eventout pg4 fsmc_a14 eventout pg5 fsmc_a15 eventout pg6 fsmc_int2 eventout pg7 usart6_ck fsmc_int3 eventout pg8 usart6_rts eth _pps_out eventout pg9 usart6_rx fsmc_ne2/ fsmc_nce3 eventout pg10 fsmc_nce4_1/ fsmc_ne3 eventout pg11 eth _mii_tx_en eth _rmii_tx_en fsmc_nce4_2 eventout pg12 usart6_rts fsmc_ne4 eventout pg13 uart6_cts eth _mii_txd0 eth _rmii_txd0 fsmc_a24 eventout pg14 usart6_tx eth _mii_txd1 eth _rmii_txd1 fsmc_a25 eventout pg15 usart6_cts dcmi_d13 eventout ph0 - osc_in ph1 - osc_out ph2 eth _mii_crs eventout ph3 eth _mii_col eventout ph4 i2c2_scl otg_hs_ulpi_nxt eventout ph5 i2c2_sda eventout ph6 i2c2_smba tim12_ch1 eth _mii_rxd2 eventout ph7 i2c3_scl eth _mii_rxd3 eventout ph8 i2c3_sda dcmi_hsync eventout ph9 i2c3_smba tim12_ch2 dcmi_d0 eventout ph10 tim5_ch1 dcmi_d1 eventout ph11 tim5_ch2 dcmi_d2 eventout ph12 tim5_ch3 dcmi_d3 eventout ph13 tim8_ch1n can1_tx eventout table 7. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/i2c2/i2c3 spi1/spi2/i2s2 spi3/i2s3 usart1/2/3 uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_hs dcmi
pinouts and pin description stm32f21xxx 56/173 doc id 17050 rev 8 ph14 tim8_ch2n dcmi_d4 eventout ph15 tim8_ch3n dcmi_d11 eventout pi0 tim5_ch4 spi2_nss i2s2_ws dcmi_d13 eventout pi1 spi2_sck i2s2_sck dcmi_d8 eventout pi2 tim8_ch4 spi2_miso dcmi_d9 eventout pi3 tim8_etr spi2_mosi i2s2_sd dcmi_d10 eventout pi4 tim8_bkin dcmi_d5 eventout pi5 tim8_ch1 dcmi_vsync eventout pi6 tim8_ch2 dcmi_d6 eventout pi7 tim8_ch3 dcmi_d7 eventout pi8 pi9 can1_rx eventout pi10 eth _mii_rx_er eventout pi11 otg_hs_ulpi_dir eventout table 7. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/i2c2/i2c3 spi1/spi2/i2s2 spi3/i2s3 usart1/2/3 uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_hs dcmi
stm32f21xxx memory mapping doc id 17050 rev 8 57/173 4 memory mapping the memory map is shown in figure 13 .
memory mapping stm32f21xxx 58/173 doc id 17050 rev 8 figure 13. memory map 512-mbyte block 7 cortex-m3's internal peripherals 512-mbyte block 6 not used 512-mbyte block 5 fsmc registers 512-mbyte block 4 fsmc bank 3 & bank4 512-mbyte block 3 fsmc bank1 & bank2 512-mbyte block 2 peripherals 512-mbyte block 1 sram 0x0000 0000 0x1fff ffff 0x2000 0000 0x3fff ffff 0x4000 0000 0x5fff ffff 0x6000 0000 0x7fff ffff 0x8000 0000 0x9fff ffff 0xa000 0000 0xbfff ffff 0xc000 0000 0xdfff ffff 0xe000 0000 0xffff ffff 512-mbyte block 0 code flash 0x0810 0000 - 0x0fff ffff 0x1fff 0000 - 0x1fff 7a0f 0x1fff c000 - 0x1fff c007 0x0800 0000 - 0x080f ffff 0x0001 c000 - 0x07ff ffff 0x0000 0000 - 0x000f ffff system memory + otp reserved reserved aliased to flash, system memory or sram depending on the boot pins sram (16 kb aliased by bit-banding) reserved 0x2000 0000 - 0x2001 bfff 0x2001 c000 - 0x2001 ffff 0x2002 0000 - 0x3fff ffff tim2 tim3 0x4000 0000 - 0x4000 03ff tim4 tim5 tim6 tim7 reserved 0x4000 0400 - 0x4000 07ff 0x4000 0800 - 0x4000 0bff 0x4000 0c00 - 0x4000 0fff 0x4000 1000 - 0x4000 13ff 0x4000 2000 - 0x4000 23ff 0x4000 2400 - 0x4000 27ff rtc & bkp registers 0x4000 2800 - 0x4000 2bff wwdg 0x4000 2c00 - 0x4000 2fff iwdg 0x4000 3000 - 0x4000 33ff reserved 0x4000 3400 - 0x4000 37ff spi2/i2s2 0x4000 3800 - 0x4000 3bff spi3/i2s3 0x4000 3c00 - 0x4000 3fff reserved 0x4000 4000 - 0x4000 43ff usart2 0x4000 4400 - 0x4000 47ff 0x4000 4800 - 0x4000 4bff usart3 uart4 0x4000 4c00 - 0x4000 4fff uart5 0x4000 5000 - 0x4000 53ff i2c1 0x4000 5400 - 0x4000 57ff i2c2 0x4000 5800 - 0x4000 5bff reserved 0x4000 6c00 - 0x4000 6fff 0x4000 7000 - 0x4000 73ff pwr 0x4000 7400 - 0x4000 77ff dac1/dac2 0x4000 7800 - 0x4000 ffff tim1 / pwm1 0x4001 0000 - 0x4001 03ff tim8 / pwm2 0x4001 0400 - 0x4001 07ff port a usart1 0x4001 1000 - 0x4001 13ff 0x4001 1400 - 0x4001 17ff port b 0x4001 1800 - 0x4001 1fff port c 0x4001 2000 - 0x4001 23ff port d 0x4001 2400 - 0x4001 27ff port e 0x4001 2800 - 0x4001 2bff port f 0x4001 2c00 - 0x4001 2fff port g 0x4001 3000 - 0x4001 33ff reserved 0x4001 3400 - 0x4001 37ff 0x4001 3800 - 0x4001 3bff 0x4001 4000 - 0x4001 43ff 0x4001 4400 - 0x4001 47ff usart6 0x4001 4800 - 0x4001 4bff reserved 0x4002 000 - 0x4002 03ff 0x4002 0c00 - 0x4002 0fff 0x4002 1000 - 0x4002 13ff 0x4002 1400 - 0x4002 17ff reset clock controller (rcc) 0x4002 1800 - 0x4002 1bff port h 0x4002 1c00 - 0x4002 1fff flash interface 0x4002 2000 - 0x4002 23ff reserved 0x4002 2400 - 0x4002 2fff crc 0x4002 3000 - 0x4002 33ff reserved 0x5006 0c00 - 0x5fff ffff fsmc bank1 nor/psram 1 0x6000 0000 - 0x63ff ffff fsmc bank1 nor/psram 2 0x6400 0000 - 0x67ff ffff fsmc bank1 nor/psram 3 0x6800 0000 - 0x6bff ffff fsmc bank1 nor/psram 4 0x6c00 0000 - 0x6fff ffff fsmc bank2 nand (nand1) 0x7000 0000 - 0x7fff ffff fsmc bank3 nand (nand2) 0x8000 0000 - 0x8fff ffff fsmc bank4 pc card 0x9000 0000 - 0x9fff ffff fsmc control register 0xa000 0000 - 0xa000 0fff reserved 0xa000 1000 - 0xbfff ffff ai15989c option bytes tim10 syscfg 0x4002 0400 - 0x4002 07ff 0x4002 0800 - 0x4002 0bff sdio reserved reserved 0x4001 4c00 - 0x4001 ffff exti 0x4001 3c00 - 0x4001 3fff reserved bxcan2 0x4000 6000 - 0x4000 63ff 0x4000 6400 - 0x4000 67ff 0x4000 6800 - 0x4000 6bff 0x5006 0800 - 0x5006 0fff rng 0x5006 0400 - 0x5006 07ff hash 0x5006 0000 - 0x5006 03ff cryp 0x5005 0400 - 0x5005 0fff reserved 0x5005 0000 - 0x5005 03ff dcmi 0x5004 0000 - 0x5004 0fff reserved 0x5000 0000 - 0x5003 ffff usb otg fs 0x4002 9400 - 0x4fff ffff reserved 0x4004 0000 - 0x4007 ffff usb otg hs reserved 0x4002 9400 - 0x4003 ffff 0x4002 8000 - 0x4002 93ff ethernet reserved 0x4002 6800 - 0x4002 7fff 0x4002 6400 - 0x4002 67ff 0x4002 6000 - 0x4002 63ff dma2 dma1 reserved 0x4002 5000 - 0x4002 5fff 0x4002 4000 - 0x4002 4fff bkpsram 0x4002 3c00 - 0x4002 3fff 0x4002 3800 - 0x4002 3bff reserved 0x4002 3400 - 0x4002 37ff port i tim11 tim9 spi1 adc1 - adc2 - adc3 reserved bxcan1 0x4000 5c00 - 0x4000 5fff i2c3 reserved tim12 tim13 tim14 0x4000 1c00 - 0x4000 1fff 0x4000 1800 - 0x4000 1bff 0x4000 1400 - 0x4000 17ff sram (112 kb aliased by bit-banding) reserved 0x1fff c008 - 0x1fff ffff 0x1fff 7a10 - 0x1fff 7fff reserved reserved
stm32f21xxx electrical characteristics doc id 17050 rev 8 59/173 5 electrical characteristics 5.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 5.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 5.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 1.8 v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 5.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 14 . 5.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 15 . figure 14. pin loading condition s figure 15. pin input voltage ms19011v1 c = 50 pf stm32f pin osc_out (hi-z when using hse or lse) ms19010v1 stm32f pin v in osc_out (hi-z when using hse or lse)
electrical characteristics stm32f21xxx 60/173 doc id 17050 rev 8 5.1.6 power supply scheme figure 16. power supply scheme 1. each power supply pair must be decoupled with filtering ceramic c apacitors as shown above. these capacitors must be placed as close as possible to , or below, the appropriate pins on the undersi de of the pcb to ensure the good functionality of the device. 2. to connect regoff pin, refer to section 2.2.16: voltage regulator . 3. the two 2.2 f ceramic capacitors should be replaced by tw o 100 nf decoupling capacitors when the voltage regulator is off. 4. the 4.7 f ceramic capacitor must be connected to one of the v dd pin. ms19041v2 v dd 1/2/...14/15 an alo g: rcs, pll, ... po wer swi tch v bat gp i/os out in kernel logic (cpu, digital & ram) backup circuitry (osc32k,rtc, backup registers, backup ram) wakeup logic 15 100 nf + 1 4.7 f 1.8-3.6 v voltage regulator v ss 1/2/...14/15 v dda v ref+ v ref- v ssa adc level shifter io logic v dd 100 nf + 1 f v ref 100 nf + 1 f v dd flash memory v cap_1 v cap_2 2 2.2 f regoff
stm32f21xxx electrical characteristics doc id 17050 rev 8 61/173 5.1.7 current con sumption measurement figure 17. current consumption measurement scheme 5.2 absolute maximum ratings stresses above the absolute maximum ratings listed in ta bl e 8: voltage characteristics , ta bl e 9: current characteristics , and ta bl e 10: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. ai14126 v bat v dd v dda i dd _v bat i dd table 8. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda , v dd ) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ?0.3 4.0 v v in input voltage on five-volt tolerant pin (2) 2. v in maximum value must always be respected. refer to table 9 for the values of the maximum allowed injected current. v ss ?0.3 v dd +4 input voltage on any other pin v ss ?0.3 4.0 | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins - 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 5.3.14: absolute maximum ratings (electrical sensitivity)
electrical characteristics stm32f21xxx 62/173 doc id 17050 rev 8 5.3 operating conditions 5.3.1 general operating conditions table 9. current characteristics symbol ratings max. unit i vdd total current into v dd power lines (source) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 120 ma i vss total current out of v ss ground lines (sink) (1) 120 i io output current sunk by any i/o and control pin 25 output current source by any i/os and control pin 25 i inj(pin) (2) 2. negative injection disturbs the analog performance of the device. see note in section 5.3.20: 12-bit adc characteristics . injected current on five-volt tolerant i/o (3) 3. positive injection is not possible on thes e i/os. a negative injection is induced by v in v dd while a negative inje ction is induced by v in stm32f21xxx electrical characteristics doc id 17050 rev 8 63/173 v cap1 internal core voltage to be supplied externally in regoff mode 1.1 1.3 v v cap2 p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (3) lqfp64 - 444 mw lqfp100 - 434 lqfp144 - 500 lqfp176 - 526 ufbga176 - 513 t a ambient temperature for 6 suffix version maximum power dissipation ?40 85 c low power dissipation (4) ?40 105 ambient temperature for 7 suffix version maximum power dissipation ?40 105 c low power dissipation (4) ?40 125 t j junction temperature range 6 suffix version ?40 105 c 7 suffix version ?40 125 1. when the adc is used, refer to table 63: adc characteristics . 2. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and power-down operation. 3. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax . 4. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax . table 11. general operating conditions (continued) symbol parameter conditions min max unit table 12. limitations depending on the operating power supply range operating power supply range adc operation maximum flash memory access frequency (f flashmax ) number of wait states at maximum cpu frequency (f cpumax = 120 mhz) (1) i/o operation fsmc_clk frequency for synchronous accesses possible flash memory operations v dd =1.8 to 2.1 v conversion time up to 1 msps 16 mhz with no flash memory wait state 7 (2) ? degraded speed performance ? no i/o compensation up to 30 mhz 8-bit erase and program operations only v dd = 2.1 to 2.4 v conversion time up to 1 msps 18 mhz with no flash memory wait state 6 (2) ? degraded speed performance ? no i/o compensation up to 30 mhz 16-bit erase and program operations
electrical characteristics stm32f21xxx 64/173 doc id 17050 rev 8 v dd = 2.4 to 2.7 v conversion time up to 2 msps 24 mhz with no flash memory wait state 4 (2) ? degraded speed performance ? i/o compensation works up to 48 mhz 16-bit erase and program operations v dd = 2.7 to 3.6 v (3) conversion time up to 2 msps 30 mhz with no flash memory wait state 3 (2) ? full-speed operation ? i/o compensation works ?up to 60 mhz when v dd = 3.0 to 3.6 v ?up to 48 mhz when v dd = 2.7 to 3.0 v 32-bit erase and program operations 1. the number of wait states can be reduced by reducing the cpu frequency (see figure 18 ). 2. thanks to the art accelerator and the 128-bit flash memory , the number of wait states given here does not impact the execution speed from flash memory since the art accelerator al lows to achieve a performance equivalent to 0 wait state program execution. 3. the voltage range for otg usb fs can drop down to 2.7 v. however it is degraded between 2.7 and 3 v. table 12. limitations depending on the operating power supply range operating power supply range adc operation maximum flash memory access frequency (f flashmax ) number of wait states at maximum cpu frequency (f cpumax = 120 mhz) (1) i/o operation fsmc_clk frequency for synchronous accesses possible flash memory operations
stm32f21xxx electrical characteristics doc id 17050 rev 8 65/173 figure 18. number of wait states versus f cpu and v dd range 5.3.2 vcap1/vcap2 external capacitor stabilization for the main regulato r is achieved by connecting an external capacitor to the vcap1/vcap2 pins. c ext is specified in ta bl e 13 . figure 19. external capacitor c ext 1. legend: esr is the equivalent series resistance. ai18748b 0 1 2 3 4 5 6 7 8 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 104 108 11 2 11 6 120 number of wait states fcpu (mhz) wait states vs fcpu and vdd range 1.8 to 2.1v 2.1 to 2.4v 2.4 to 2.7v 2.7 to 3.6v table 13. vcap1/vcap2 operating conditions (1) 1. when bypassing the voltage regulator, the two 2.2 f v cap capacitors are not required and should be replaced by two 100 nf decoupling capacitors. symbol parameter conditions cext capacitance of external capacitor 2.2 f esr esr of external capacitor < 2 m s 19044v1 e s r r le a k c
electrical characteristics stm32f21xxx 66/173 doc id 17050 rev 8 5.3.3 operating conditions at power- up / power-down (regulator on) subject to general operating conditions for t a . table 14. operating conditions at power-up / power-down (regulator on) 5.3.4 operating conditions at power- up / power-down (regulator off) subject to general operating conditions for t a . table 15. operating conditions at power-up / power-down (regulator off) symbol parameter min max unit t vdd v dd rise time rate 20 s/v v dd fall time rate 20 symbol parameter conditions min max unit t vdd v dd rise time rate power-up 20 s/v v dd fall time rate power-down 20 t vcap v cap_1 and v cap_2 rise time rate power-up 20 v cap_1 and v cap_2 fall time rate power-down 20
stm32f21xxx electrical characteristics doc id 17050 rev 8 67/173 5.3.5 embedded reset and power control block characteristics the parameters given in ta bl e 16 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 11 . table 16. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.09 2.14 2.19 v pls[2:0]=000 (falling edge) 1.98 2.04 2.08 v pls[2:0]=001 (rising edge) 2.23 2.30 2.37 v pls[2:0]=001 (falling edge) 2.13 2.19 2.25 v pls[2:0]=010 (rising edge) 2.39 2.45 2.51 v pls[2:0]=010 (falling edge) 2.29 2.35 2.39 v pls[2:0]=011 (rising edge) 2.54 2.60 2.65 v pls[2:0]=011 (falling edge) 2.44 2.51 2.56 v pls[2:0]=100 (rising edge) 2.70 2.76 2.82 v pls[2:0]=100 (falling edge) 2.59 2.66 2.71 v pls[2:0]=101 (rising edge) 2.86 2.93 2.99 v pls[2:0]=101 (falling edge) 2.65 2.84 3.02 v pls[2:0]=110 (rising edge) 2.96 3.03 3.10 v pls[2:0]=110 (falling edge) 2.85 2.93 2.99 v pls[2:0]=111 (rising edge) 3.07 3.14 3.21 v pls[2:0]=111 (falling edge) 2.95 3.03 3.09 v v pvdhyst (2) pvd hysteresis - 100 - mv v por/pdr power-on/power-down reset threshold falling edge 1.60 (1) 1.68 1.76 v rising edge 1.64 1.72 1.80 v v pdrhyst (2) pdr hysteresis - 40 - mv
electrical characteristics stm32f21xxx 68/173 doc id 17050 rev 8 5.3.6 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pin loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 17: current consumption measurement scheme . all run mode current consumption measurements given in this section are performed using coremark code. v bor1 brownout level 1 threshold falling edge 2.13 2.19 2.24 v rising edge 2.23 2.29 2.33 v v bor2 brownout level 2 threshold falling edge 2.44 2.50 2.56 v rising edge 2.53 2.59 2.63 v v bor3 brownout level 3 threshold falling edge 2.75 2.83 2.88 v rising edge 2.85 2.92 2.97 v borhyst (2) bor hysteresis - 100 - mv t rsttempo (2)(3) reset temporization 0.5 1.5 3.0 ms i rush (2) inrush current on voltage regulator power-on (por or wakeup from standby) - 160 200 ma e rush (2) inrush energy on voltage regulator power-on (por or wakeup from standby) v dd = 1.8 v, t a = 105 c, i rush = 171 ma for 31 s --5.4c 1. the product behavior is guaranteed by design down to the minimum v por/pdr value. 2. guaranteed by design, not tested in production. 3. the reset temporization is measured from the power-on (p or reset or wakeup from v bat ) to the instant when first instruction is read by the user application code. table 16. embedded reset and power control block characteristics (continued) symbol parameter conditions min typ max unit
stm32f21xxx electrical characteristics doc id 17050 rev 8 69/173 typical and maximum current consumption the mcu is placed under the following conditions: at startup, all i/o pins are configured as analog inputs by firmware. all peripherals are disabled except if it is explicitly mentioned. the flash memory access time is adjusted to f hclk frequency (0 wait state from 0 to 30 mhz, 1 wait state from 30 to 60 mhz, 2 wait states from 60 to 90 mhz and 3 wait states from 90 to 120 mhz). when the peripherals are enabled hclk is the system clock, f pclk1 = f hclk /4, and f pclk2 = f hclk /2, except is explicitly mentioned. the maximum values are obtained for v dd = 3.6 v and maximum ambient temperature (t a ), and the typical values for t a = 25 c and v dd = 3.3 v unless otherwise specified. table 17. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator disabled) symbol parameter conditions f hclk typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock (2) , all peripherals enabled (3) 120 mhz 61 81 93 ma 90 mhz 48 68 80 60 mhz 33 53 65 30 mhz 18 38 50 25 mhz 14 34 46 16 mhz (4) 10 30 42 8 mhz 6 26 38 4 mhz 4 24 36 2 mhz 3 23 35 external clock (2) , all peripherals disabled 120 mhz 33 54 66 90 mhz 27 47 59 60 mhz 19 39 51 30 mhz 11 31 43 25 mhz 8 28 41 16 mhz (4) 62638 8 mhz 4 24 36 4 mhz 3 23 35 2 mhz 2 23 34 1. based on characterization, tested in production at v dd max and f hclk max with peripherals enabled. 2. external clock is 4 mhz and pll is on when f hclk > 25 mhz. 3. when the adc is on (adon bit set in the adc_cr2 register), add an additional power consumption of 1.6 ma per adc for the analog part. 4. in this case hclk = system clock/2.
electrical characteristics stm32f21xxx 70/173 doc id 17050 rev 8 table 18. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabled) or ram (1) symbol parameter conditions f hclk typ max (2) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock (3) , all peripherals enabled (4) 120 mhz 49 63 72 ma 90 mhz 38 51 61 60 mhz 26 39 49 30 mhz 14 27 37 25 mhz 11 24 34 16 mhz (5) 82130 8 mhz 5 17 27 4 mhz 3 16 26 2 mhz 2 15 25 external clock (3) , all peripherals disabled 120 mhz 21 34 44 90 mhz 17 30 40 60 mhz 12 25 35 30 mhz 7 20 30 25 mhz 5 18 28 16 mhz (5) 4.0 17.0 27.0 8 mhz 2.5 15.5 25.5 4 mhz 2.0 14.7 24.8 2 mhz 1.6 14.5 24.6 1. code and data processing running from sram1 using boot pins. 2. based on characterization, tested in production at v dd max and f hclk max with peripherals enabled. 3. external clock is 4 mhz and pll is on when f hclk > 25 mhz. 4. when the adc is on (adon bit set in t he adc_cr2 register), add an additional powe r consumption of 1.6 ma per adc for the analog part. 5. in this case hclk = system clock/2.
stm32f21xxx electrical characteristics doc id 17050 rev 8 71/173 figure 20. typical current consumption vs temperature, run mode, code with data processing running from ram, and peripherals on figure 21. typical current consumption vs temperature, run mode, code with data processing running from ram, and peripherals off ms19014v1 0 10 20 30 40 50 60 0 20406080100120 cpu frequnecy (mhz) 105c 85c 70c 55c 30c 0c -45c i dd(run) (ma) ms19015v1 0 5 10 15 20 25 30 0 20 40 60 80 100 120 cpu frequency (mhz ) 105c 85c 70c 55c 30c 0c -45c i dd(run) (ma)
electrical characteristics stm32f21xxx 72/173 doc id 17050 rev 8 figure 22. typical current consumption vs temperature, run mode, code with data processing running from flash, art accelerator off, peripherals on figure 23. typical current consumption vs temperature, run mode, code with data processing running from flash, art accelerator off, peripherals off ms19016v1 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 0 20 40 60 80 100 120 105 85 30c -45c i dd(run) (ma) cpu frequnecy (mhz) ms19017v1 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 cpu frequency (mhz ) 105 85 30c -45c i dd(run) (ma)
stm32f21xxx electrical characteristics doc id 17050 rev 8 73/173 table 19. typical and maximum current consumption in sleep mode symbol parameter conditions f hclk typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in sleep mode external clock (2) , all peripherals enabled (3) 120 mhz 38 51 61 ma 90 mhz 30 43 53 60 mhz 20 33 43 30 mhz 11 25 35 25 mhz 8 21 31 16 mhz 6 19 29 8 mhz 3.6 17.0 27.0 4 mhz 2.4 15.4 25.3 2 mhz 1.9 14.9 24.7 external clock (2) , all peripherals disabled 120 mhz 8 21 31 90 mhz 7 20 30 60 mhz 5 18 28 30 mhz 3.5 16.0 26.0 25 mhz 2.5 16.0 25.0 16 mhz 2.1 15.1 25.0 8 mhz 1.7 15.0 25.0 4 mhz 1.5 14.6 24.6 2 mhz 1.4 14.2 24.3 1. based on characterization, tested in production at v dd max and f hclk max with peripherals enabled. 2. external clock is 4 mhz and pll is on when f hclk > 25 mhz. 3. add an additional power cons umption of 1.6 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register).
electrical characteristics stm32f21xxx 74/173 doc id 17050 rev 8 figure 24. typical current consumption vs temperature in sleep mode, peripherals on figure 25. typical current consumption vs temperature in sleep mode, peripherals off ms19018v1 0 5 10 15 20 25 30 35 40 45 50 0 20 40 60 80 100 120 105c 85c 70c 55c 30c 0c -45c idd (sleep) (ma) cpu frequency (mhz) ms19019v1 0 2 4 6 8 10 12 14 16 0 20406080100120 105c 85c 70c 55c 30c 0c -45c cpu frequency (mhz) idd (sleep) (ma)
stm32f21xxx electrical characteristics doc id 17050 rev 8 75/173 figure 26. typical current consumption vs temperature in stop mode 1. all typical and maximum values from table 18 and figur e 26 will be reduced over ti me by up to 50% as part of st continuous improvement of test procedures. new versions of the datasheet will be released to reflect these changes table 20. typical and maximum current consumptions in stop mode (1) symbol parameter conditions typ max unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c i dd_stop supply current in stop mode with main regulator in run mode flash in stop mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 0.55 1.2 11.00 20.00 ma flash in deep power down mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 0.50 1.2 11.00 20.00 supply current in stop mode with main regulator in low power mode flash in stop mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 0.35 1.1 8.00 15.00 flash in deep power down mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 0.30 1.1 8.00 15.00 1. all typical and maximum values will be further reduced by up to 50% as par t of st continuous improvement of test procedures. new versions of the datasheet will be released to reflect these changes. ms19020v1 0.01 0.1 1 10 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 temperature (c) idd_stop_mr_flhstop idd_stop_mr_flhdeep idd_stop_lp_flhstop idd_stop_lp_flhdeep i dd(stop) (ma)
electrical characteristics stm32f21xxx 76/173 doc id 17050 rev 8 on-chip peripheral current consumption the current consumption of the on-chip peripherals is given in ta bl e 23 . the mcu is placed under the following conditions: table 21. typical and maximum current consumptions in standby mode symbol parameter conditions typ max (1) unit t a = 25 c t a = 85 c t a = 105 c v dd = 1.8 v v dd = 2.4 v v dd = 3.3 v v dd = 3.6 v i dd_stby supply current in standby mode backup sram on, low-speed oscillator and rtc on 3.0 3.4 4.0 15.1 25.8 a backup sram off, low- speed oscillator and rtc on 2.4 2.7 3.3 12.4 20.5 backup sram on, rtc off 2.4 2.6 3.0 12.5 24.8 backup sram off, rtc off 1.7 1.9 2.2 9.8 19.2 1. based on characterization, not tested in production. table 22. typical and maximum current consumptions in v bat mode symbol parameter conditions typ max (1) unit t a = 25 c t a = 85 c t a = 105 c v dd = 1.8 v v dd = 2.4 v v dd = 3.3 v v dd = 3.6 v i dd_vbat backup domain supply current backup sram on, low-speed oscillator and rtc on 1.29 1.42 1.68 12 19 a backup sram off, low-speed oscillator and rtc on 0.62 0.73 0.96 8 10 backup sram on, rtc off 0.79 0.81 0.86 9 16 backup sram off, rtc off 0.10 0.10 0.10 5 7 1. based on characterization, not tested in production.
stm32f21xxx electrical characteristics doc id 17050 rev 8 77/173 at startup, all i/o pins are configured as analog inputs by firmware. all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with one peripheral clocked on (with only the clock applied) the code is running from flash memory and the flash memory access time is equal to 3 wait states at 120 mhz prefetch and cache on when the peripherals are enabled, hclk = 120mhz, f pclk1 = f hclk /4, and f pclk2 = f hclk /2 the typical values are obtained for v dd = 3.3 v and t a = 25 c, unless otherwise specified. table 23. peripheral current consumption peripheral (1) typical consumption at 25 c unit ahb1 gpio a 0.45 ma gpio b 0.43 gpio c 0.46 gpio d 0.44 gpio e 0.44 gpio f 0.42 gpio g 0.44 gpio h 0.42 gpio i 0.43 otg_hs + ulpi 3.64 crc 1.17 bkpsram 0.21 dma1 2.76 dma2 2.85 eth_mac + eth_mac_tx eth_mac_rx eth_mac_ptp 2.99 ahb2 otg_fs 3.16 dcmi 0.60 ahb3 fsmc 1.74 ahb2 crypto 0.39 ma hash 0.50 rng 0.43
electrical characteristics stm32f21xxx 78/173 doc id 17050 rev 8 apb1 tim2 0.61 ma tim3 0.49 tim4 0.54 tim5 0.62 tim6 0.20 tim7 0.20 tim12 0.36 tim13 0.28 tim14 0.25 usart2 0.25 usart3 0.25 uart4 0.25 uart5 0.26 i2c1 0.25 i2c2 0.25 i2c3 0.25 spi2 0.20/0.10 spi3 0.18/0.09 can1 0.31 can2 0.30 dac channel 1 (2) 1.11 dac channel 1 (3) 1.11 pwr 0.15 wwdg 0.15 table 23. peripheral current consumption (continued) peripheral (1) typical consumption at 25 c unit
stm32f21xxx electrical characteristics doc id 17050 rev 8 79/173 5.3.7 wakeup time from low-power mode the wakeup times given in ta bl e 24 is measured on a wakeup phase with a 16 mhz hsi rc oscillator. the clock source used to wake up the device depe nds from the current operating mode: stop or standby mode: the cloc k source is the rc oscillator sleep mode: the clock source is the clock that was set before entering sleep mode. all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 11 . apb2 sdio 0.69 ma tim1 1.06 tim8 1.03 tim9 0.58 tim10 0.37 tim11 0.39 adc1 (4) 2.13 adc2 (4) 2.04 adc3 (4) 2.12 spi1 1.20 usart1 0.38 usart6 0.37 1. external clock is 25 mhz (hse oscillat or with 25 mhz crystal) and pll is on. 2. en1 bit is set in dac_cr register. 3. en2 bit is set in dac_cr register. 4. f adc = f pclk2 /2, adon bit set in adc_cr2 register. table 23. peripheral current consumption (continued) peripheral (1) typical consumption at 25 c unit table 24. low-power mode wakeup timings symbol parameter min (1) typ (1) max (1) unit t wusleep (2) wakeup from sleep mode - 1 - s t wustop (2) wakeup from stop mode (regulator in run mode) - 13 - s wakeup from stop mode (regulator in low power mode) - 17 40 wakeup from stop mode (regulator in low power mode and flash memory in deep power down mode) -110- t wustdby (2)(3) wakeup from standby mode 260 375 480 s 1. based on characterization, not tested in production. 2. the wakeup times are measured from the wakeup event to the point in which the application c ode reads the first instruction. 3. t wustdby minimum and maximum values are given at 105 c and ?45 c, respectively.
electrical characteristics stm32f21xxx 80/173 doc id 17050 rev 8 5.3.8 external cloc k source characteristics high-speed external user clock generated from an external source the characteristics given in ta b l e 25 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in ta b l e 11 . low-speed external user clock generated from an external source the characteristics given in ta b l e 26 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in ta b l e 11 . table 25. high-speed external user clock characteristics symbol parameter conditions min typ max unit f hse_ext external user clock source frequency (1) 1-26mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 1. guaranteed by design, not tested in production. 5-- ns t r(hse) t f(hse) osc_in rise or fall time (1) --20 c in(hse) osc_in input capacitance (1) -5-pf ducy (hse) duty cycle 45 - 55 % i l osc_in input leakage current v ss v in v dd --1a table 26. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lse) t f(lse) osc32_in high or low time (1) 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time (1) --50 c in(lse) osc32_in input capacitance (1) -5-pf ducy (lse) duty cycle 30 - 70 % i l osc32_in input leakage current v ss v in v dd --1a
stm32f21xxx electrical characteristics doc id 17050 rev 8 81/173 figure 27. high-speed external clock source ac timing diagram figure 28. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 26 mhz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 27 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). a i1752 8 o s c_in extern a l s tm 3 2f clock s o u rce v h s eh t f(h s e) t w(h s e) i l 90 % 10 % t h s e t t r(h s e) t w(h s e) f h s e_ext v h s el a i17529 o s c 3 2_in extern a l s tm 3 2f clock s o u rce v l s eh t f(l s e) t w(l s e) i l 90 % 10 % t l s e t t r(l s e) t w(l s e) f l s e_ext v l s el
electrical characteristics stm32f21xxx 82/173 doc id 17050 rev 8 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 29 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . note: for information on electing the crystal, refer to the applicatio n note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. figure 29. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 28 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). table 27. hse 4-26 mhz oscillator characteristics (1) (2) 1. resonator characte ristics given by the crystal/ ceramic resonator manufacturer. 2. based on characterization , not tested in production. symbol parameter conditions min typ max unit f osc_in oscillator frequency 4 - 26 mhz r f feedback resistor - 200 - k i dd hse current consumption v dd =3.3 v, esr= 30 ? , c l =5 pf@25 mhz -449- a v dd =3.3 v, esr= 30 ? , c l =10 pf@25 mhz -532- g m oscillator transconductance startup 5 - - ma/v t su(hse (3) 3. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonat or and it can vary significantly with the crystal manufacturer startup time v dd is stabilized - 2 - ms a i175 3 0 o s c_ou t o s c_in f h s e c l1 r f s tm 3 2f 8 mh z re s on a tor re s on a tor with integr a ted c a p a citor s bi as controlled g a in r ext (1) c l2
stm32f21xxx electrical characteristics doc id 17050 rev 8 83/173 note: for c l1 and c l2 it is recommended to use high-quality external ceramic capacitors in the 5 pf to 15 pf range selected to match the requirements of the crystal or resonator (see figure 30 ). c l1 and c l2, are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . load capacitance c l has the following formula: c l = c l1 x c l2 / (c l1 + c l2 ) + c stray where c stray is the pin capacitance and board or trace pcb-related capacitance. typically, it is between 2 pf and 7 pf. note: for information on electing the crystal, refer to the applicatio n note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. caution: to avoid exceeding the maximum value of c l1 and c l2 (15 pf) it is strongly recommended to use a resonator with a load capacitance c l 7 pf. never use a resonator with a load capacitance of 12.5 pf. example: if you choose a resonator with a load capacitance of c l = 6 pf, and c stray = 2 pf, then c l1 = c l2 = 8 pf. figure 30. typical application with a 32.768 khz crystal table 28. lse oscillator characteristics (f lse = 32.768 khz) (1) 1. guaranteed by design, not tested in production. symbol parameter conditions min typ max unit r f feedback resistor - 18.4 - m i dd lse current consumption - - 1 a g m oscillator transconductance 2.8 - - a/v t su(lse) (2) 2. t su(lse) is the startup time measured from the mom ent it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. th is value is measured for a standard cr ystal resonator and it can vary significantly with t he crystal manufacturer startup time v dd is stabilized - 2 - s a i175 3 1 o s c 3 2_ou t o s c 3 2_in f l s e c l1 r f s tm 3 2f 3 2.76 8 kh z re s on a tor re s on a tor with integr a ted c a p a citor s bi as controlled g a in c l2
electrical characteristics stm32f21xxx 84/173 doc id 17050 rev 8 5.3.9 internal clock source characteristics the parameters given in ta bl e 29 and ta b l e 30 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 11 . high-speed internal (hsi) rc oscillator figure 31. acc hsi versus temperature table 29. hsi oscillator characteristics (1) 1. v dd = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - 16 - mhz acc hsi accuracy of the hsi oscillator user-trimmed with the rcc_cr register (2) 2. refer to application note an2868 ?stm32f10xxx internal rc oscillator (hsi) calibrat ion? available from the st website www.st.com. --1% factory- calibrated t a = ?40 to 105 c ?8 - 4.5 % t a = ?10 to 85 c ?4 - 4 % t a = 25 c ?1 - 1 % t su(hsi) (3) 3. guaranteed by design, not tested in production. hsi oscillator startup time -2.24 s i dd(hsi) hsi oscillator power consumption -6080a ms19012v2 -8 -6 -4 -2 0 2 4 6 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 normalized deviation (%) temperature (c) max avg min
stm32f21xxx electrical characteristics doc id 17050 rev 8 85/173 low-speed internal (lsi) rc oscillator figure 32. acc lsi versus temperature 5.3.10 pll characteristics the parameters given in ta bl e 31 and ta b l e 32 are derived from tests performed under temperature and v dd supply voltage conditions summarized in ta b l e 11 . table 30. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi (2) 2. based on characterization , not tested in production. frequency 17 32 47 khz t su(lsi) (3) 3. guaranteed by design, not tested in production. lsi oscillator startup time - 15 40 s i dd(lsi) (3) lsi oscillator power consumption - 0.4 0.6 a ms19013v1 -40 -30 -20 -10 0 10 20 30 40 50 -45-35-25-15-5 5 152535455565758595105 nor m ali zed devi ati on (%) te m p e r at u r e ( c) max avg min table 31. main pll characteristics symbol parameter conditions min typ max unit f pll_in pll input clock (1) 0.95 (2) 12.10 (2) mhz f pll_out pll multiplier output clock 24 - 120 mhz f pll48_out 48 mhz pll multiplier output clock -- 48mhz f vco_out pll vco output 192 - 432 mhz
electrical characteristics stm32f21xxx 86/173 doc id 17050 rev 8 t lock pll lock time vco freq = 192 mhz 75 - 200 s vco freq = 432 mhz 100 - 300 jitter (3) cycle-to-cycle jitter system clock 120 mhz rms - 25 - ps peak to peak - 150 - period jitter rms - 15 - peak to peak - 200 - main clock output (mco) for rmii ethernet cycle to cycle at 50 mhz on 1000 samples -32 - main clock output (mco) for mii ethernet cycle to cycle at 25 mhz on 1000 samples -40 - bit time can jitter cycle to cycle at 1 mhz on 1000 samples - 330 - i dd(pll) (4) pll power consumption on vdd vco freq = 192 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(pll) (4) pll power consumption on vdda vco freq = 192 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 ma 1. take care of using the appropriate division factor m to obtain the specified pll input clock values. the m factor is shared between pll and plli2s. 2. guaranteed by design, not tested in production. 3. the use of 2 plls in parallel could degraded the jitter up to +30%. 4. based on characterization, not tested in production. table 31. main pll characteristics (continued) symbol parameter conditions min typ max unit table 32. plli2s (audio pll) characteristics symbol parameter conditions min typ max unit f plli2s_in plli2s input clock (1) 0.95 (2) 12.10 (2) mhz f plli2s_out plli2s multiplier output clock - - 216 mhz f vco_out plli2s vco output 192 - 432 mhz t lock plli2s lock time vco freq = 192 mhz 75 - 200 s vco freq = 432 mhz 100 - 300
stm32f21xxx electrical characteristics doc id 17050 rev 8 87/173 jitter (3) master i2s clock jitter cycle to cycle at 12.288 mhz on 48khz period, n=432, r=5 rms - 90 - peak to peak - 280 - ps average frequency of 12.288 mhz n=432, r=5 on 1000 samples -90 -ps ws i2s clock jitter cycle to cycle at 48 khz on 1000 samples -400 - ps i dd(plli2s) (4) plli2s power consumption on v dd vco freq = 192 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(plli2s) (4) plli2s power consumption on v dda vco freq = 192 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 ma 1. take care of using the appropriate division fact or m to have the specified pll input clock values. 2. guaranteed by design, not tested in production. 3. value given with main pll running. 4. based on characterization, not tested in production. table 32. plli2s (audio pll) characteristics (continued) symbol parameter conditions min typ max unit
electrical characteristics stm32f21xxx 88/173 doc id 17050 rev 8 5.3.11 pll spread spectrum clock generation (sscg) characteristics the spread spectrum clock generation (sscg) feature allows to reduce electromagnetic interferences (see ta bl e 39: emi characteristics ). it is available only on the main pll. equation 1 the frequency mo dulation period (modeper) is gi ven by the equation below: f pll_in and f mod must be expressed in hz. as an example: if f pll_in = 1 mhz and f mod = 1 khz, the modulation depth (modeper) is given by equation 1: equation 2 equation 2 allows to calculate the increment step (incstep): f vco_out must be expressed in mhz. with a modulation depth (md) = 2 % (4 % peak to peak), and plln = 240 (in mhz): an amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of modper and incstep. as a result, the achieved modulation depth is quantized. the percentage quantized modulation depth is given by the following formula: as a result: table 33. sscg parameters constraint symbol parameter min typ max (1) unit f mod modulation frequency - - 10 khz md peak modulation depth 0.25 - 2 % modeper * incstep - - 2 15 ? 1- 1. guaranteed by design, not tested in production. modeper round f pll_in 4f mod () ? [] = modeper round 10 6 410 3 () ? [] 250 == incstep round 2 15 1 ? () md plln () 100 5 modeper () ? [] = incstep round 2 15 1 ? () 2 240 () 100 5 250 () ? [] 126md(quantitazed)% == md quantized % modeper incstep 100 5 () 2 15 1 ? () plln () ? = md quantized % 250 126 100 5 () 2 15 1 ? () 240 () ? 2.0002%(peak) ==
stm32f21xxx electrical characteristics doc id 17050 rev 8 89/173 figure 33 and figure 34 show the main pll output clock waveforms in center spread and down spread modes, where: f0 is f pll_out nominal. t mode is the modulation period. md is the modulation depth. figure 33. pll output clock waveforms in center spread mode figure 34. pll output clock waveforms in down spread mode 5.3.12 memory characteristics flash memory the characteristics are given at t a = ? 40 to 105 c unless otherwise specified. frequency (pll_out) time f0 tmode 2*tmode md ai17291 md frequency (pll_out) time f0 tmode 2*tmode 2*md ai17292 table 34. flash memory characteristics symbol parameter conditions min typ max unit i dd supply current write / erase 8-bit mode v dd = 1.8 v -5- ma write / erase 16-bit mode v dd = 2.1 v -8- write / erase 32-bit mode v dd = 3.3 v -12-
electrical characteristics stm32f21xxx 90/173 doc id 17050 rev 8 table 35. flash memory programming symbol parameter conditions min (1) typ max (1) 1. based on characterization , not tested in production. unit t prog word programming time program/erase parallelism (psize) = x 8/16/32 -16100 (2) 2. the maximum programming time is m easured after 100k erase operations. s t erase16kb sector (16 kb) erase time program/erase parallelism (psize) = x 8 - 400 800 ms program/erase parallelism (psize) = x 16 - 300 600 program/erase parallelism (psize) = x 32 - 250 500 t erase64kb sector (64 kb) erase time program/erase parallelism (psize) = x 8 - 1200 2400 ms program/erase parallelism (psize) = x 16 - 700 1400 program/erase parallelism (psize) = x 32 - 550 1100 t erase128kb sector (128 kb) erase time program/erase parallelism (psize) = x 8 -24 s program/erase parallelism (psize) = x 16 -1.32.6 program/erase parallelism (psize) = x 32 -12 t me mass erase time program/erase parallelism (psize) = x 8 -1632 s program/erase parallelism (psize) = x 16 -1122 program/erase parallelism (psize) = x 32 -816 v prog programming voltage 32-bit program operation 2.7 - 3.6 v 16-bit program operation 2.1 - 3.6 v 8-bit program operation 1.8 - 3.6 v table 36. flash memory programming with v pp symbol parameter conditions min (1) typ max (1) unit t prog double word programming t a = 0 to +40 c v dd = 3.3 v v pp = 8.5 v - 16 100 (2) s t erase16kb sector (16 kb) erase time - 230 - ms t erase64kb sector (64 kb) erase time - 490 - t erase128kb sector (128 kb) erase time - 875 - t me mass erase time - 6.9 - s v prog programming voltage 2.7 - 3.6 v
stm32f21xxx electrical characteristics doc id 17050 rev 8 91/173 table 37. flash memory endurance and data retention 5.3.13 emc characteristics susceptibility tests ar e performed on a sample basis during device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in ta b l e 38 . they are based on the ems levels and classes defined in application note an1709. v pp v pp voltage range 7 - 9 v i pp minimum current sunk on the v pp pin 10 - - ma t vpp (3) cumulative time during which v pp is applied - - 1 hour 1. guaranteed by design, not tested in production. 2. the maximum programming time is m easured after 100k erase operations. 3. v pp should only be connected du ring programming/erasing. symbol parameter conditions value unit min (1) 1. based on characterization , not tested in production. n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over t he whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20 table 36. flash memory programming with v pp (continued) symbol parameter conditions min (1) typ max (1) unit
electrical characteristics stm32f21xxx 92/173 doc id 17050 rev 8 designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application, executing eembc ? code, is running. this emission te st is compliant wi th sae iec61967-2 standard which specifies the test board and the pin loading. table 38. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp100, t a = +25 c, f hclk = 75 mhz, conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp100, t a = +25 c, f hclk = 75 mhz, conforms to iec 61000-4-2 4a
stm32f21xxx electrical characteristics doc id 17050 rev 8 93/173 5.3.14 absolute maximum rati ngs (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determine its perfor mance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. static latch-up two complementary static tests are required on six parts to assess the latch-up performance: a supply overvoltage is applied to each power supply pin a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. table 39. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f cpu ] unit 8/120 mhz s emi peak level v dd = 3.3 v, t a = 25 c, lqfp176 package, conforming to sae j1752/3 eembc, code running with art enabled 0.1 to 30 mhz 21 dbv 30 to 130 mhz 28 130 mhz to 1ghz 31 sae emi level 4 - v dd = 3.3 v, t a = 25 c, lqfp176 package, conforming to sae j1752/3 eembc, code running with art enabled, pll spread spectrum enabled 0.1 to 30 mhz 21 dbv 30 to 130 mhz 15 130 mhz to 1ghz 14 sae emi level 3.5 - table 40. esd absolute maximum ratings symbol ratings conditions class maximum value (1) unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c conforming to jesd22-a114 2 2000 (2) v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c conforming to jesd22-c101 ii 500 1. based on characterization results, not tested in production. 2. on v bat pin, v esd(hbm) is limited to 1000 v.
electrical characteristics stm32f21xxx 94/173 doc id 17050 rev 8 5.3.15 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection a ccidentally happens, susceptibilit y tests are performed on a sample basis during device characterization. functional susceptibilty to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode. while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (>5 lsb tue), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). the test results are given in ta b l e 42 . table 41. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a table 42. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on all ft pins ?5 +0 ma injected current on any other pin ?5 +5
stm32f21xxx electrical characteristics doc id 17050 rev 8 95/173 5.3.16 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in ta bl e 43 are derived from tests performed under the conditions summarized in ta b l e 11 . all i/os are cmos and ttl compliant. table 43. i/o static characteristics symbol parameter conditions min typ max unit v il input low level voltage ttl ports 2.7 v v dd 3.6 v v ss ?0.3 - 0.8 v v ih (1) tt (2) i/o input high level voltage 2.0 - v dd +0.3 ft (3) i/o input high level voltage 2.0 - 5.5 v il input low level voltage cmos ports 1.8 v v dd 3.6 v v ss ?0.3 - 0.3v dd v ih (1) tt i/o input high level voltage 0.7v dd -3.6 (4) ft i/o input high level voltage -5.2 (4) cmos ports 2.0 v v dd 3.6 v -5.5 (4) v hys i/o schmitt trigger voltage hysteresis (5) -200- mv io ft schmitt trigger voltage hysteresis (5) 5% v dd (4) - - i lkg i/o input leakage current (6) v ss v in v dd -- 1 a i/o ft input leakage current (6) v in = 5 v - - 3 r pu weak pull-up equivalent resistor (7) all pins except for pa10 and pb12 v in = v ss 30 40 50 k pa10 and pb12 81115 r pd weak pull-down equivalent resistor all pins except for pa10 and pb12 v in = v dd 30 40 50 pa10 and pb12 81115 c io (8) i/o pin capacitance 5 pf 1. if v ih maximum value cannot be respected, the inject ion current must be limited externally to i inj(pin) maximum value. 2. tt = 3.6 v tolerant. 3. ft = 5 v tolerant. 4. with a minimum of 100 mv. 5. hysteresis voltage between schmitt trigger switching leve ls. based on characterization, not tested in production. 6. leakage could be higher than the maximum value, if negative current is injected on adjacent pins. 7. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this mos/nmos contribution to the series resistance is minimum (~10% order) . 8. guaranteed by design, not tested in production.
electrical characteristics stm32f21xxx 96/173 doc id 17050 rev 8 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. output driving current the gpios (general purpose input/outputs) can sink or source up to 8 ma, and sink or source up to 20 ma (with a relaxed v ol /v oh ) except pc13, pc14 and pc15 which can sink or source up to 3ma. when using the pc13 to pc15 gpios in output mode, the speed should not exceed 2 mhz with a maximum load of 30 pf. in the user application, the number of i/o pins which can drive current must be limited to respect the absolute maxi mum rating specified in section 5.2 : the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see ta bl e 9 ). the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see ta b l e 9 ). output voltage levels unless otherwise specified, the parameters given in ta bl e 44 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 11 . all i/os are cmos and ttl compliant. table 44. output voltage characteristics (1) 1. pc13, pc14, pc15 and pi8 are supplied through the power switch. since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 and pi8 in output mode is limited: the speed should not exceed 2 mhz with a maximum load of 30 pf and these i/os must not be used as a current source (e.g. to drive an led). symbol parameter conditions min max unit v ol (2) 2. the i io current sunk by the device must always re spect the absolute maximu m rating specified in table 9 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin when 8 pins are sunk at same time cmos ports i io = +8 ma 2.7 v < v dd < 3.6 v -0.4 v v oh (3) 3. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 9 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?0.4 - v ol (2) output low level voltage for an i/o pin when 8 pins are sunk at same time ttl ports i io =+ 8ma 2.7 v < v dd < 3.6 v -0.4 v v oh (3) output high level voltage for an i/o pin when 8 pins are sourced at same time 2.4 - v ol (2)(4) output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +20 ma 2.7 v < v dd < 3.6 v -1.3 v v oh (3)(4) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?1.3 - v ol (2)(4) output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +6 ma 2 v < v dd < 2.7 v -0.4 v v oh (3)(4) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?0.4 -
stm32f21xxx electrical characteristics doc id 17050 rev 8 97/173 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 35 and ta bl e 45 , respectively. unless otherwise specified, the parameters given in ta bl e 45 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 11 . 4. based on characterization data, not tested in production. table 45. i/o ac characteristics (1)(2) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit 00 f max(io)out maximum frequency (3) c l = 50 pf, v dd > 2.70 v - - 2 mhz c l = 50 pf, v dd > 1.8 v - - 2 c l = 10 pf, v dd > 2.70 v - - tbd c l = 10 pf, v dd > 1.8 v - - tbd t f(io)out output high to low level fall time c l = 50 pf, v dd = 1.8 v to 3.6 v --tbd ns t r(io)out output low to high level rise time --tbd 01 f max(io)out maximum frequency (3) c l = 50 pf, v dd > 2.70 v - - 25 mhz c l = 50 pf, v dd > 1.8 v - - 12.5 (4) c l = 10 pf, v dd > 2.70 v - - 50 (4) c l = 10 pf, v dd > 1.8 v - - tbd t f(io)out output high to low level fall time c l = 50 pf, v dd < 2.7 v - - tbd ns c l = 10 pf, v dd > 2.7 v - - tbd t r(io)out output low to high level rise time c l = 50 pf, v dd < 2.7 v - - tbd c l = 10 pf, v dd > 2.7 v - - tbd 10 f max(io)out maximum frequency (3) c l = 40 pf, v dd > 2.70 v - - 50 (4) mhz c l = 40 pf, v dd > 1.8 v - - 25 c l = 10 pf, v dd > 2.70 v - - 100 (4) c l = 10 pf, v dd > 1.8 v - - tbd t f(io)out output high to low level fall time c l = 50 pf, 2.4 < v dd < 2.7 v - - tbd ns c l = 10 pf, v dd > 2.7 v - - tbd t r(io)out output low to high level rise time c l = 50 pf, 2.4 < v dd < 2.7 v - - tbd c l = 10 pf, v dd > 2.7 v - - tbd
electrical characteristics stm32f21xxx 98/173 doc id 17050 rev 8 figure 35. i/o ac characteristics definition 11 f max(io)out maximum frequency (3) c l = 30 pf, v dd > 2.70 v - - 100 (4) mhz c l = 30 pf, v dd > 1.8 v - - 50 (4) c l = 10 pf, v dd > 2.70 v - - 200 (4) c l = 10 pf, v dd > 1.8 v - - tbd t f(io)out output high to low level fall time c l = 20 pf, 2.4 < v dd < 2.7 v - - tbd ns c l = 10 pf, v dd > 2.7 v - - tbd t r(io)out output low to high level rise time c l = 20 pf, 2.4 < v dd < 2.7 v - - tbd c l = 10 pf, v dd > 2.7 v - - tbd -t extipw pulse width of external signals detected by the exti controller 10 - - ns 1. the i/o speed is configured using the ospeedry[1:0] bi ts. refer to the stm32f20/21xxx reference manual for a description of the gpiox_speedr gpio port output speed register. 2. tbd stands for ?to be defined?. 3. the maximum frequency is defined in figure 35 . 4. for maximum frequencies above 50 mhz, the compensation cell should be used. table 45. i/o ac characteristics (1)(2) (continued) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit ai14131 10% 90% 50% t r(io)out output ext ernal on 50pf maximum frequency is achieved if (t r + t f ) ?? 2/3)t and if the duty cycle is (45-55%) ? 10 % 50% 90% when loaded by 50pf t t r(io)out
stm32f21xxx electrical characteristics doc id 17050 rev 8 99/173 5.3.17 nrst pin characteristics the nrst pin input driver uses cmos techno logy. it is connected to a permanent pull-up resistor, r pu (see ta bl e 43 ). unless otherwise specified, the parameters given in ta bl e 46 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 11 . figure 36. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 46 . otherwise the reset is not taken into account by the device. table 46. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) nrst input low level voltage ttl ports 2.7 v v dd 3.6 v v ss ? 0.3 - 0.8 v v ih(nrst) (1) nrst input high level voltage 2 - v dd +0.3 v il(nrst) (1) nrst input low level voltage cmos ports 1.8 v v dd 3.6 v v ss ? 0.3 - 0.3v dd v v ih(nrst) (1) nrst input high level voltage 0.7v dd -v dd +0.3 v hys(nrst) nrst schmitt trigger voltage hysteresis - 200 - mv r pu weak pull-up equivalent resistor (2) v in = v ss 30 40 50 k v f(nrst) (1) nrst input filtered pulse - - 100 ns v nf(nrst) (1) nrst input not filtered pulse v dd > 2.7 v 300 - - ns t nrst_out generated reset pulse duration internal reset source 20 - - s 1. guaranteed by design, not tested in production. 2. the pull-up is designed with a true resistance in se ries with a switchable pmos . this pmos contribution to the series resistance must be minimum (~10% order) . ai14132c stm32fxxx r pu nrst (2) v dd filter internal reset 0.1 f external reset circuit (1)
electrical characteristics stm32f21xxx 100/173 doc id 17050 rev 8 5.3.18 tim time r characteristics the parameters given in ta bl e 47 and ta b l e 48 are guaranteed by design. refer to section 5.3.16: i/o port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output). table 47. characteristics of timx connected to the apb1 domain (1) 1. timx is used as a general term to refer to the tim2, tim3, tim4, tim5, tim6, tim7, and tim12 timers. symbol parameter conditions min max unit t res(tim) timer resolution time ahb/apb1 prescaler distinct from 1, f timxclk = 60 mhz 1- t timxclk 16.7 - ns ahb/apb1 prescaler = 1, f timxclk = 30 mhz 1- t timxclk 33.3 - ns f ext timer external clock frequency on ch1 to ch4 f timxclk = 60 mhz apb1= 30 mhz 0 f timxclk /2 mhz 030mhz res tim timer resolution - 16/32 bit t counter 16-bit counter clock period when internal clock is selected 1 65536 t timxclk 0.0167 1092 s 32-bit counter clock period when internal clock is selected 1- t timxclk 0.0167 71582788 s t max_count maximum possible count - 65536 65536 t timxclk -71.6 s
stm32f21xxx electrical characteristics doc id 17050 rev 8 101/173 5.3.19 communications interfaces i 2 c interface characteristics unless otherwise specified, the parameters given in ta bl e 49 are derived from tests performed under the ambient temperature, f pclk1 frequency and v dd supply voltage conditions summarized in ta bl e 11 . stm32f215xx and stm32f217xx i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: the i/o pins sda and scl are mapped to are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in ta b l e 49 . refer also to section 5.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl) . table 48. characteristics of timx connected to the apb2 domain (1) 1. timx is used as a general term to refer to the tim1, tim8, tim9, tim10, and tim11 timers. symbol parameter conditions min max unit t res(tim) timer resolution time ahb/apb2 prescaler distinct from 1, f timxclk = 120 mhz 1- t timxclk 8.3 - ns ahb/apb2 prescaler = 1, f timxclk = 60 mhz 1- t timxclk 16.7 - ns f ext timer external clock frequency on ch1 to ch4 f timxclk = 120 mhz apb2 = 60 mhz 0 f timxclk /2 mhz 060mhz res tim timer resolution - 16 bit t counter 16-bit counter clock period when internal clock is selected 1 65536 t timxclk 0.0083 546 s t max_count maximum possible count - 65536 65536 t timxclk - 35.79 s
electrical characteristics stm32f21xxx 102/173 doc id 17050 rev 8 table 49. i 2 c characteristics symbol parameter standard mode i 2 c (1) 1. guaranteed by design, not tested in production. fast mode i 2 c (1)(2) 2. f pclk1 must be at least 2 mhz to achieve standard mode i 2 c frequencies. it must be at least 4 mhz to achieve fast mode i 2 c frequencies, and a multiple of 10 mhz to reach the 400 khz maximum i 2 c fast mode clock. unit min max min max t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time 0 - 0 900 (3) 3. the maximum data hold time has only to be met if the interface does not stretch the low period of the scl signal. t r(sda) t r(scl) sda and scl rise time - 1000 20 + 0.1c b 300 t f(sda) t f(scl) sda and scl fall time - 300 - 300 t h(sta) start condition hold time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - s t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - s c b capacitive load for each bus line - 400 - 400 pf
stm32f21xxx electrical characteristics doc id 17050 rev 8 103/173 figure 37. i 2 c bus ac waveforms and measurement circuit 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . table 50. scl frequency (f pclk1 = 30 mhz.,v dd = 3.3 v) (1)(2) 1. r p = external pull-up resistance, f scl = i 2 c speed, 2. for speeds around 200 khz, the tole rance on the achieved speed is of 5%. for other speed ranges, the tolerance on the achieved speed 2%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) i2c_ccr value r p = 4.7 k 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012c 20 0x02ee ai14979b start sd a 100 4.7k i2c bus 4.7k 100 v dd v dd stm32fxx sda scl t f(sda) t r(sda) scl t h(sta) t w(sclh) t w(scll) t su(sda) t r(scl) t f(scl) t h(sda) s tart repeated start t su(sta) t su(sto) stop t w(sto:sta)
electrical characteristics stm32f21xxx 104/173 doc id 17050 rev 8 i 2 s - spi interface characteristics unless otherwise specified, the parameters given in ta bl e 51 for spi or in ta bl e 52 for i 2 s are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in ta bl e 11 . refer to section 5.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi and ws, ck, sd for i 2 s). table 51. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency spi1 master/slave mode - 30 mhz spi2/spi3 master/slave mode - 15 t r(scl) t f(scl) spi clock rise and fall time capacitive load: c = 30 pf, f pclk = 30 mhz - 8ns ducy(sck) spi slave input clock duty cycle slave mode 30 70 % t su(nss) (1) 1. based on characterization , not tested in production. nss setup time slave mode 4t pclk - ns t h(nss) (1) nss hold time slave mode 2t pclk - t w(sclh) (1) t w(scll) (1) sck high and low time master mode, f pclk = 30 mhz, presc = 2 t pclk - 3t pclk +3 t su(mi) (1) t su(si) (1) data input setup time master mode 5 - slave mode 5 - t h(mi) (1) t h(si) (1) data input hold time master mode 5 - slave mode 4 - t a(so) (1)(2) 2. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. data output access time slave mode, f pclk = 30 mhz 0 3t pclk t dis(so) (1)(3) 3. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z data output disable time slave mode 2 10 t v(so) (1) data output valid time slave mode (after enable edge) - 25 t v(mo) (1) data output valid time master mode (after enable edge) - 5 t h(so) (1) data output hold time slave mode (after enable edge) 15 - t h(mo) (1) master mode (after enable edge) 2 -
stm32f21xxx electrical characteristics doc id 17050 rev 8 105/173 figure 38. spi timing diagram - slave mode and cpha = 0 figure 39. spi timing diagram - slave mode and cpha = 1 ai14134c sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input
electrical characteristics stm32f21xxx 106/173 doc id 17050 rev 8 figure 40. spi timing diagram - master mode ai14136 sck input cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo)
stm32f21xxx electrical characteristics doc id 17050 rev 8 107/173 table 52. i 2 s characteristics symbol parameter conditions min max unit f ck 1/t c(ck) i 2 s clock frequency master, 16-bit data, audio frequency = 48 khz, main clock disabled 1.23 1.24 mhz slave 0 64f s (1) t r(ck) t f(ck) i 2 s clock rise and fall time capacitive load c l = 50 pf - (2) ns t v(ws) (3) ws valid time master 0.3 - t h(ws) (3) ws hold time master 0 - t su(ws) (3) ws setup time slave 3 - t h(ws) (3) ws hold time slave 0 - t w(ckh) (3) t w(ckl) (3) ck high and low time master f pclk = 30 mhz 396 - t su(sd_mr) (3) t su(sd_sr) (3) data input setup time master receiver slave receiver 45 0 - t h(sd_mr) (3)(4) t h(sd_sr) (3)(4) data input hold time master receiver: f pclk = 30 mhz, slave receiver: f pclk = 30 mhz 13 0 - t v(sd_st) (3)(4) data output valid time slave transmitter (after enable edge) - 30 t h(sd_st) (3) data output hold time slave transmitter (after enable edge) 10 - t v(sd_mt) (3)(4) data output valid time master transmitter (after enable edge) - 6 t h(sd_mt) (3) data output hold time master transmitter (after enable edge) 0- 1. f s is the sampling frequency. refer to the i2s section of t he stm32f20xxx/21xxx reference manual for more details. f ck values reflect only the digital periphera l behavior which leads to a minimum of (i2sdiv/(2*i2sdiv+odd), a maximum of (i2sdiv+odd)/(2*i2sdiv+odd) and f s maximum values for each mode/condition. 2. refer to table 45: i/o ac characteristics . 3. based on design simulation and/or characte rization results, not tested in production. 4. depends on f pclk . for example, if f pclk =8 mhz, then t pclk = 1/f plclk =125 ns.
electrical characteristics stm32f21xxx 108/173 doc id 17050 rev 8 figure 41. i 2 s slave timing diagram (philips protocol) (1) 1. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. figure 42. i 2 s master timing diagram (philips protocol) (1) 1. based on characterization , not tested in production. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. ck inp u t cpol = 0 cpol = 1 t c(ck) w s inp u t s d tr a n s mit s d receive t w(ckh) t w(ckl) t su (w s ) t v( s d_ s t) t h( s d_ s t) t h(w s ) t su ( s d_ s r) t h( s d_ s r) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14 88 1 b l s b receive (2) l s b tr a n s mit (2) ck o u tp u t cpol = 0 cpol = 1 t c(ck) w s o u tp u t s d receive s d tr a n s mit t w(ckh) t w(ckl) t su ( s d_mr) t v( s d_mt) t h( s d_mt) t h(w s ) t h( s d_mr) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14 88 4 b t f(ck) t r(ck) t v(w s ) l s b receive (2) l s b tr a n s mit (2)
stm32f21xxx electrical characteristics doc id 17050 rev 8 109/173 usb otg fs characteristics the usb otg interface is usb-if certified (full-spee d). this interface is present in both the usb otg hs and usb otg fs controllers. table 53. usb otg fs startup time symbol parameter max unit t startup (1) 1. guaranteed by design, not tested in production. usb otg fs transceiver startup time 1 s table 54. usb otg fs dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. typ. max. (1) unit input levels v dd usb otg fs operating voltage 3.0 (2) 2. the stm32f215xx and stm32f217xx usb otg fs functi onality is ensured down to 2.7 v but not the full usb otg fs electrical c haracteristics which are degraded in the 2.7-to-3.0 v v dd voltage range. -3.6v v di (3) 3. guaranteed by design, not tested in production. differential input sensitivity i(usb_fs_dp/dm, usb_hs_dp/dm) 0.2 - - v v cm (3) differential common mode range includes v di range 0.8 - 2.5 v se (3) single ended receiver threshold 1.3 - 2.0 output levels v ol static output level low r l of 1.5 k to 3.6 v (4) 4. r l is the load connected on the usb otg fs drivers --0.3 v v oh static output level high r l of 15 k to v ss (4) 2.8 - 3.6 r pd pa11, pa12, pb14, pb15 (usb_fs_dp/dm, usb_hs_dp/dm) v in = v dd 17 21 24 k pa9, pb13 (otg_fs_vbus, otg_hs_vbus) 0.65 1.1 2.0 r pu pa12, pb15 (usb_fs_dp, usb_hs_dp) v in = v ss 1.5 1.8 2.1 pa9, pb13 (otg_fs_vbus, otg_hs_vbus) v in = v ss 0.25 0.37 0.55
electrical characteristics stm32f21xxx 110/173 doc id 17050 rev 8 figure 43. usb otg fs timings: definiti on of data signal rise and fall time usb hs characteristics ta bl e 56 shows the usb hs operating voltage. table 55. usb otg fs electrical characteristics (1) 1. guaranteed by design, not tested in production. driver characteristics symbol parameter conditions min max unit t r rise time (2) 2. measured from 10% to 90% of the data signal. for more detailed informations, please refer to usb specification - chapt er 7 (version 2.0). c l = 50 pf 420ns t f fall time (2) c l = 50 pf 4 20 ns t rfm rise/ fall time matching t r /t f 90 110 % v crs output signal crossover voltage 1.3 2.0 v table 56. usb hs dc electrical characteristics symbol parameter min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input level v dd usb otg hs operating voltage 2.7 3.6 v table 57. clock timing parameters parameter (1) 1. guaranteed by design, not tested in production. symbol min nominal max unit frequency (first transition) 8-bit 10% f start_8bit 54 60 66 mhz frequency (steady state) 500 ppm f steady 59.97 60 60.03 mhz duty cycle (first transition) 8-bit 10% d start_8bit 40 50 60 % duty cycle (steady state) 500 ppm d steady 49.975 50 50.025 % time to reach the stea dy state frequency and duty cycle after the first transition t steady --1.4ms clock startup time after the de-assertion of suspendm peripheral t start_dev --5.6 ms host t start_host --- phy preparation time after the first transition of the input clock t prep ---s ai14137 t f differen tial data lines v ss v cr s t r crossover points
stm32f21xxx electrical characteristics doc id 17050 rev 8 111/173 figure 44. ulpi timing diagram ethernet characteristics ta bl e 59 shows the ethernet operating voltage. ta bl e 60 gives the list of ethernet mac signals for the smi (station management interface) and figure 45 shows the corresponding timing diagram. table 58. ulpi timing symbol parameter value (1) 1. v dd = 2.7 v to 3.6 v and t a = ?40 to 85 c. unit min. max. t sc control in (ulpi_dir) setup time - 2.0 ns control in (ulpi_nxt) setup time - 1.5 t hc control in (ulpi_dir, ulpi_nxt) hold time 0 - t sd data in setup time - 2.0 t hd data in hold time 0 - t dc control out (ulpi_stp) setup time and hold time - 9.2 t dd data out available from clock rising edge - 10.7 table 59. ethernet dc electrical characteristics symbol parameter min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input level v dd ethernet operating voltage 2.7 3.6 v clock control in (ulpi_dir, ulpi_nxt) data in (8-bit) control out (ulpi_stp) data out (8-bit) t dd t dc t hd t sd t hc t sc ai17361c t dc
electrical characteristics stm32f21xxx 112/173 doc id 17050 rev 8 figure 45. ethernet smi timing diagram ta bl e 61 gives the list of ethernet mac signals for the rmii and figure 46 shows the corresponding timing diagram. figure 46. ethernet rmii timing diagram table 60. dynamics characteristics: ethernet mac signals for smi symbol rating min typ max unit t mdc mdc cycle time (2.38 mhz) 411 420 425 ns t d(mdio) mdio write data valid time 6 10 13 ns t su(mdio) read data setup time 12 - - ns t h(mdio) read data hold time 0 - - ns table 61. dynamics characteristics: ethernet mac signals for rmii symbol rating min typ max unit t su(rxd) receive data setup time 1 - - ns t ih(rxd) receive data hold time 1.5 - - t su(crs) carrier sense set-up time 0 - - t ih(crs) carrier sense hold time 2 - - t d(txen) transmit enable valid delay time 9 11 13 t d(txd) transmit data valid delay time 9 11.5 14 eth_mdc eth_mdio(o) eth_mdio(i) t mdc t d(mdio) t su(mdio) t h(mdio) ai15666d rmii_ref_clk rmii_tx_en rmii_txd[1:0] rmii_rxd[1:0] rmii_crs_dv t d(txen) t d(txd) t su(rxd) t su(crs) t ih(rxd) t ih(crs) ai15667
stm32f21xxx electrical characteristics doc id 17050 rev 8 113/173 ta bl e 62 gives the list of ethernet mac signals for mii and figure 46 shows the corresponding timing diagram. figure 47. ethernet mii timing diagram can (controller area network) interface refer to section 5.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (cantx and canrx). table 62. dynamics characteristics: ethernet mac signals for mii symbol rating min typ max unit t su(rxd) receive data setup time 7.5 - - ns t ih(rxd) receive data hold time 1 - - ns t su(dv) data valid setup time 4 - - ns t ih(dv) data valid hold time 0 - - ns t su(er) error setup time 3.5 - - ns t ih(er) error hold time 0 - - ns t d(txen) transmit enable valid delay time - 11 14 ns t d(txd) transmit data valid delay time - 11 14 ns mii_rx_clk mii_rxd[3:0] mii_rx_dv mii_rx_er t d(txen) t d(txd) t su(rxd) t su(er) t su(dv) t ih(rxd) t ih(er) t ih(dv) ai15668 mii_tx_clk mii_tx_en mii_txd[3:0]
electrical characteristics stm32f21xxx 114/173 doc id 17050 rev 8 5.3.20 12-bit adc characteristics unless otherwise specified, the parameters given in ta bl e 63 are derived from tests performed under the ambient temperature, f pclk2 frequency and v dda supply voltage conditions summarized in ta bl e 11 . table 63. adc characteristics symbol parameter conditions min typ max unit v dda power supply 1.8 - 3.6 v v ref+ positive reference voltage 1.8 (1) -v dda v f adc adc clock frequency v dda = 1.8 to 2.4 v 0.6 - 15 mhz v dda = 2.4 to 3.6 v 0.6 - 30 mhz f trig (2) external trigger frequency f adc = 30 mhz with 12-bit resolution - - 1764 khz --171/f adc v ain conversion voltage range (3) 0 (v ssa or v ref- tied to ground) -v ref+ v r ain (2) external input impedance see equation 1 for details --50k r adc (2)(4) sampling switch resistance 1.5 - 6 k c adc (2) internal sample and hold capacitor -4-pf t lat (2) injection trigger conversion latency f adc = 30 mhz - - 0.100 s --3 (5) 1/f adc t latr (2) regular trigger conversion latency f adc = 30 mhz - - 0.067 s --2 (5) 1/f adc t s (2) sampling time f adc = 30 mhz 0.100 - 16 s 3 - 480 1/f adc t stab (2) power-up time - 2 3 s t conv (2) total conversion time (including sampling time) f adc = 30 mhz 12-bit resolution 0.5 - 16.40 s f adc = 30 mhz 10-bit resolution 0.43 - 16.34 s f adc = 30 mhz 8-bit resolution 0.37 - 16.27 s f adc = 30 mhz 6-bit resolution 0.3 - 16.20 s 9 to 492 (t s for sampling +n-bit re solution for successive approximation) 1/f adc
stm32f21xxx electrical characteristics doc id 17050 rev 8 115/173 equation 1: r ain max formula the formula above ( equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of lsb. n = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the adc_smpr1 register. a f s (2) sampling rate (f adc = 30 mhz) 12-bit resolution single adc --2msps 12-bit resolution interleave dual adc mode - - 3.75 msps 12-bit resolution interleave triple adc mode --6msps i vref+ (2) adc v ref dc current consumption in conversion mode f adc = 30 mhz 3 sampling time 12-bit resolution - 300 500 a f adc = 30 mhz 480 sampling time 12-bit resolution --16a i vdda (2) adc vdda dc current consumption in conversion mode f adc = 30 mhz 3 sampling time 12-bit resolution -1.61.8ma f adc = 30 mhz 480 sampling time 12-bit resolution --60a 1. it is recommended to maintain the voltage difference between v ref+ and v dda below 1.8 v. 2. based on characterization, not tested in production. 3. v ref+ is internally connected to v dda and v ref- is internally connected to v ssa . 4. r adc maximum value is given for v dd =1.8 v, and minimum value for v dd =3.3 v. 5. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 63 . table 63. adc characteristics (continued) symbol parameter conditions min typ max unit table 64. adc accuracy (1) symbol parameter test conditions typ max (2) unit et total unadjusted error f pclk2 = 60 mhz, f adc = 30 mhz, r ain < 10 k , v dda = 1.8 to 3.6 v 2 5 lsb eo offset error 1.5 2.5 eg gain error 1.5 3 ed differential linearity error 1 2 el integral linearity error 1.5 3 r ain k0.5 ? () f adc c adc 2 n 2 + () ln -------------------------------------------------------------- r adc ? =
electrical characteristics stm32f21xxx 116/173 doc id 17050 rev 8 note: adc accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. any positive injectio n current within the limits specified for i inj(pin) and i inj(pin) in section 5.3.16 does not affect the adc accuracy. figure 48. adc accura cy characteristics 1. example of an actual transfer curve. 2. ideal transfer curve. 3. end point correlation line. 4. e t = total unadjusted error: maximum deviation be tween the actual and the ideal transfer curves. eo = offset error: deviation between the fi rst actual transition and the first ideal one. eg = gain error: deviation between the last ideal transition and the last actual one. ed = differential linearity error: maximum dev iation between actual steps and the ideal one. el = integral linearity error: maximum deviati on between any actual tr ansition and the end point correlation line. 1. better performance could be achieved in restricted v dd , frequency and temperature ranges. 2. based on characterization , not tested in production. e o e g 1l sb ideal 4095 4094 4093 5 4 3 2 1 0 7 6 1 2 3 456 7 4093 4094 4095 4096 (1) (2) e t e d e l (3) v dda v ssa ai14395c v ref+ 4096 (or depending on package)] v dda 4096 [1lsb ideal =
stm32f21xxx electrical characteristics doc id 17050 rev 8 117/173 figure 49. typical connection diagram using the adc 1. refer to table 63 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value downgrades conversion ac curacy. to remedy this, f adc should be reduced. a i175 3 4 s tm 3 2f v dd ainx i l 1 a 0.6 v v t r ain (1) c p a r as itic v ain 0.6 v v t r adc (1) c adc (1) 12- b it converter sa mple a nd hold adc converter
electrical characteristics stm32f21xxx 118/173 doc id 17050 rev 8 general pcb design guidelines power supply decoupling should be performed as shown in figure 50 or figure 51 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed them as close as possible to the chip. figure 50. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ and v ref? inputs are both available on ufbga176 package. v ref+ is also available on all packages except for lqfp64. when v ref+ and v ref? are not available, they ar e internally connected to v dda and v ssa . figure 51. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ and v ref? inputs are both available on ufbga176 package. v ref+ is also available on all packages except for lqfp64. when v ref+ and v ref? are not available, they ar e internally connected to v dda and v ssa . v ref+ s tm 3 2f v dda v ss a /v ref- 1 f // 10 nf 1 f // 10 nf a i175 3 5 ( s ee note 1) ( s ee note 1) v ref+ /v dda s tm 3 2f 1 f // 10 nf v ref? /v ss a a i175 3 6 ( s ee note 1) ( s ee note 1)
stm32f21xxx electrical characteristics doc id 17050 rev 8 119/173 5.3.21 dac electrical characteristics table 65. dac characteristics symbol parameter min typ max unit comments v dda analog supply voltage 1.8 - 3.6 v v ref+ reference supply voltage 1.8 - 3.6 v v ref+ v dda v ssa ground 0 - 0 v r load (1) resistive load with buffer on 5 - - k r o (1) impedance output with buffer off -- 15 k when the buffer is off, the minimum resistive load between dac_out and v ss to have a 1% accuracy is 1.5 m c load (1) capacitive load - - 50 pf maximum capacitive load at dac_out pin (when the buffer is on). dac_out min (1) lower dac_out voltage with buffer on 0.2 - - v it gives the maximum output excursion of the dac. it corresponds to 12-bit input code (0x0e0) to (0xf1c) at v ref+ = 3.6 v and (0x1c7) to (0xe38) at v ref+ = 1.8 v dac_out max (1) higher dac_out voltage with buffer on --v dda ? 0.2 v dac_out min (1) lower dac_out voltage with buffer off -0.5 - mv it gives the maximum output excursion of the dac. dac_out max (1) higher dac_out voltage with buffer off --v ref+ ? 1lsb v i vref+ (3) dac dc v ref current consumption in quiescent mode (standby mode) - 170 240 a with no load, worst code (0x800) at v ref+ = 3.6 v in terms of dc consumption on the inputs -50 75 with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs i dda (3) dac dc v dda current consumption in quiescent mode (2) - 280 380 a with no load, middle code (0x800) on the inputs - 475 625 a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs dnl (3) differential non linearity difference between two consecutive code-1lsb) -- 0.5 lsb given for the dac in 10-bit configuration. -- 2 lsb given for the dac in 12-bit configuration.
electrical characteristics stm32f21xxx 120/173 doc id 17050 rev 8 inl (3) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023) -- 1 lsb given for the dac in 10-bit configuration. -- 4 lsb given for the dac in 12-bit configuration. offset (3) offset error (difference between measured value at code (0x800) and the ideal value = v ref+ /2) -- 10 mv given for the dac in 12-bit configuration -- 3 lsb given for the dac in 10-bit at v ref+ = 3.6 v -- 12lsb given for the dac in 12-bit at v ref+ = 3.6 v gain error (3) gain error - - 0.5 % given for the dac in 12-bit configuration t settling (3) settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when dac_out reaches final value 4lsb -3 6 s c load 50 pf, r load 5 k thd (3) total harmonic distortion buffer on -- - db c load 50 pf, r load 5 k update rate (1) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) -- 1 ms/s c load 50 pf, r load 5 k t wakeup (3) wakeup time from off state (setting the enx bit in the dac control register) -6.5 10 s c load 50 pf, r load 5 k input code between lowest and highest possible ones. psrr+ (1) power supply rejection ratio (to v dda ) (static dc measurement) - ?67 ?40 db no r load , c load = 50 pf 1. guaranteed by design, not tested in production. 2. the quiescent mode corresponds to a state where the dac ma intains a stable output level to ensure that no dynamic consumption occurs. 3. guaranteed by characterizati on, not tested in production. table 65. dac characteristics (continued) symbol parameter min typ max unit comments
stm32f21xxx electrical characteristics doc id 17050 rev 8 121/173 figure 52. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to r educe the output impedance and to dr ive external loads directly without the use of an external operational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. 5.3.22 temperature sen sor characteristics 5.3.23 v bat monitoring characteristics r load c load b u ffered/non- bu ffered dac dacx_out b u ffer(1) 12- b it digit a l to a n a log converter a i17157 table 66. ts characteristics symbol parameter min typ max unit t l (1) 1. based on characterization , not tested in production. v sense linearity with temperature - 1 2c avg_slope (1) average slope - 2.5 mv/c v 25 (1) voltage at 25 c - 0.76 v t start (2) 2. guaranteed by design, not tested in production. startup time - 6 10 s t s_temp (3)(2) 3. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 1c accuracy 10 - - s table 67. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k q ratio on v bat measurement - 2 - er (1) 1. guaranteed by design, not tested in production. error on q ?1 - +1 % t s_vbat (2)(2) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the v bat 1mv accuracy 5- -s
electrical characteristics stm32f21xxx 122/173 doc id 17050 rev 8 5.3.24 embedded reference voltage the parameters given in ta bl e 68 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 11 . 5.3.25 fsmc characteristics asynchronous waveforms and timings figure 53 through figure 56 represent asynchronous waveforms and ta b l e 69 through ta bl e 72 provide the corresponding timings. the results shown in these tables are obtained with the following fsmc configuration: addresssetuptime = 1 addressholdtime = 1 datasetuptime = 1 busturnaroundduration = 0x0 in all timing tables, the t hclk is the hclk clock period. table 68. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.18 1.21 1.24 v t s_vrefint (1) 1. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the internal reference voltage 10 - - s v rerint_s (2) 2. guaranteed by design, not tested in production. internal reference voltage spread over the temperature range v dd = 3 v - 3 5 mv t coeff (2) temperature coefficient - 30 50 ppm/c t start (2) startup time - 6 10 s
stm32f21xxx electrical characteristics doc id 17050 rev 8 123/173 figure 53. asynchronous non-multiplexed sram/psram/nor read waveforms 1. mode 2/b, c and d only. in mode 1, fsmc_nadv is not used. table 69. asynchronous non-multiplexed sram/psram/nor read timings (1)(2) 1. c l = 30 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(ne) fsmc_ne low time 2t hclk ? 0.5 2t hclk +0.5 ns t v(noe_ne) fsmc_nex low to fsmc_noe low 0.5 2.5 ns t w(noe) fsmc_noe low time 2t hclk - 1 2t hclk + 0.5 ns t h(ne_noe) fsmc_noe high to fsmc_ne high hold time 0 - ns t v(a_ne) fsmc_nex low to fsmc_a valid - 4 ns t h(a_noe) address hold time after fsmc_noe high 0 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 0.5 ns t h(bl_noe) fsmc_bl hold time after fsmc_noe high 0 - ns t su(data_ne) data to fsmc_nex high setup time t hclk + 0.5 - ns t su(data_noe) data to fsmc_noex high setup time t hclk + 2.5 - ns t h(data_noe) data hold time after fsmc_noe high 0 - ns t h(data_ne) data hold time after fsmc_nex high 0 - ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low - 2.5 ns t w(nadv ) fsmc_nadv low time - t hclk ? 0.5 ns data fsmc_ne fsmc_nbl[1:0] fsmc_d[15:0] t v(bl_ne) t h(data_ne) fsmc_noe address fsmc_a[25:0] t v(a_ne) fsmc_nwe t su(data_ne) t w(ne) ai14991c w(noe) t t v(noe_ne) t h(ne_noe) t h(data_noe) t h(a_noe) t h(bl_noe) t su(data_noe) fsmc_nadv (1) t v(nadv_ne) t w(nadv)
electrical characteristics stm32f21xxx 124/173 doc id 17050 rev 8 figure 54. asynchronous non-multiplexed sram/psram/nor write waveforms 1. mode 2/b, c and d only. in mode 1, fsmc_nadv is not used. table 70. asynchronous non-multiplexed sram/psram/nor write timings (1)(2) 1. c l = 30 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(ne) fsmc_ne low time 3t hclk 3t hclk + 4 ns t v(nwe_ne ) fsmc_nex low to fsmc_nwe low t hclk ? 0.5 t hclk + 0.5 ns t w(nwe) fsmc_nwe low time t hclk ? 0.5 t hclk + 3 ns t h(ne_nwe) fsmc_nwe high to fsmc_ne high hold time t hclk -ns t v(a_ne) fsmc_nex low to fsmc_a valid - 0 ns t h(a_nwe) address hold time after fsmc_nwe high t hclk - 3 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 0.5 ns t h(bl_nwe) fsmc_bl hold time after fsmc_nwe high t hclk ? 1 - ns t v(data_ne) data to fsmc_nex low to data valid - t hclk + 5 ns t h(data_nwe) data hold time after fsmc_nwe high t hclk +0.5 - ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low - 2 ns t w(nadv) fsmc_nadv low time - t hclk + 1.5 ns nbl data fsmc_nex fsmc_nbl[1:0] fsmc_d[15:0] t v(bl_ne) t h(data_nwe) fsmc_noe address fsmc_a[25:0] t v(a_ne) t w(nwe) fsmc_nwe t v(nwe_ne) t h(ne_nwe) t h(a_nwe) t h(bl_nwe) t v(data_ne) t w(ne) ai14990 fsmc_nadv (1) t v(nadv_ne) t w(nadv)
stm32f21xxx electrical characteristics doc id 17050 rev 8 125/173 figure 55. asynchronous multiplexed psram/nor read waveforms table 71. asynchronous multiplexed psram/nor read timings (1)(2) 1. c l = 30 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(ne) fsmc_ne low time 3t hclk -1 3t hclk +1 ns t v(noe_ne) fsmc_nex low to fsmc_noe low 2t hclk 2t hclk +0.5 ns t w(noe) fsmc_noe low time t hclk -1 t hclk +1 ns t h(ne_noe) fsmc_noe high to fsmc_ne high hold time 0 - ns t v(a_ne) fsmc_nex low to fsmc_a valid - 2 ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low 1 2.5 ns t w(nadv) fsmc_nadv low time t hclk ? 1.5 t hclk ns t h(ad_nadv) fsmc_ad(adress) valid hold time after fsmc_nadv high) t hclk -ns t h(a_noe) address hold time after fsmc_noe high t hclk -ns t h(bl_noe) fsmc_bl time after fsmc_noe high 0 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 1 ns t su(data_ne) data to fsmc_nex high setup time t hclk + 2 - ns t su(data_noe) data to fsmc_noe high setup time t hclk + 3 - ns t h(data_ne) data hold time after fsmc_nex high 0 - ns t h(data_noe) data hold time after fsmc_noe high 0 - ns nbl data fsmc_nbl[1:0] fsmc_ ad[15:0] t v(bl_ne) t h(data_ne) address fsmc_a[25:16] t v(a_ne) fsmc_nwe t v(a_ne) ai14892b address fsmc_nadv t v(nadv_ne) t w(nadv) t su(data_ne) t h(ad_nadv) fsmc_ne fsmc_noe t w(ne) t w(noe) t v(noe_ne) t h(ne_noe) t h(a_noe) t h(bl_noe) t su(data_noe) t h(data_noe)
electrical characteristics stm32f21xxx 126/173 doc id 17050 rev 8 figure 56. asynchronous multiplexed psram/nor write waveforms table 72. asynchronous multiplexed psram/nor write timings (1)(2) 1. c l = 30 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(ne) fsmc_ne low time 4t hclk -1 4t hclk +1 ns t v(nwe_ne) fsmc_nex low to fsmc_nwe low t hclk - 1 t hclk ns t w(nwe) fsmc_nwe low tim e 2t hclk 2t hclk +1 ns t h(ne_nwe) fsmc_nwe high to fsmc_ne high hold time t hclk - 1 - ns t v(a_ne) fsmc_nex low to fsmc_a valid - 0 ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low 1 2 ns t w(nadv) fsmc_nadv low time t hclk ? 2 t hclk + 2 ns t h(ad_nadv) fsmc_ad(adress) valid hold time after fsmc_nadv high) t hclk -ns t h(a_nwe) address hold time after fsmc_nwe high t hclk ? 0.5 - ns t h(bl_nwe) fsmc_bl hold time after fsmc_nwe high t hclk - 1 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 0.5 ns t v(data_nadv) fsmc_nadv high to data valid - t hclk +2 ns t h(data_nwe) data hold time after fsmc_nwe high t hclk ? 0.5 - ns nbl data fsmc_nex fsmc_nbl[1:0] fsmc_ ad[15:0] t v(bl_ne) t h(data_nwe) fsmc_noe address fsmc_a[25:16] t v(a_ne) t w(nwe) fsmc_nwe t v(nwe_ne) t h(ne_nwe) t h(a_nwe) t h(bl_nwe) t v(a_ne) t w(ne) ai14891b address fsmc_nadv t v(nadv_ne) t w(nadv) t v(data_nadv) t h(ad_nadv)
stm32f21xxx electrical characteristics doc id 17050 rev 8 127/173 synchronous waveforms and timings figure 57 through figure 60 represent synchronous waveforms and ta bl e 74 through ta bl e 76 provide the corresponding timings. the results shown in these tables are obtained with the following fsmc configuration: burstaccessmode = fsmc_burstaccessmode_enable; memorytype = fsmc_memorytype_cram; writeburst = fsmc_writeburst_enable; clkdivision = 1; (0 is not supported, see the stm32f20xxx/21xxx reference manual) datalatency = 1 for nor flash; datalatency = 0 for psram in all timing tables, the t hclk is the hclk clock period. figure 57. synchronous multiplexed nor/psram read timings fsmc_clk fsmc_nex fsmc_nadv fsmc_a[25:16] fsmc_noe fsmc_ad[15:0] ad[15:0] d1 d2 fsmc_nwait (waitcfg = 1b, waitpol + 0b) fsmc_nwait (waitcfg = 0b, waitpol + 0b) t w(clk) t w(clk) data latency = 0 busturn = 0 t d(clkl-nexl) t d(clkl-nexh) t d(clkl-nadvl) t d(clkl-av) t d(clkl-nadvh) t d(clkl-aiv) t d(clkh-noel) t d(clkl-noeh) t d(clkl-adv) t d(clkl-adiv) t su(adv-clkh) t h(clkh-adv) t su(adv-clkh) t h(clkh-adv) t su(nwaitv-clkh) t h(clkh-nwaitv) t su(nwaitv-clkh) t h(clkh-nwaitv) t su(nwaitv-clkh) t h(clkh-nwaitv) ai14893h
electrical characteristics stm32f21xxx 128/173 doc id 17050 rev 8 table 73. synchronous multiplexed nor/psram read timings (1)(2) 1. c l = 30 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(clk) fsmc_clk period 2t hclk -ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x=0..2) - 0 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x= 0?2) 1 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 1.5 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 2.5 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x=16?25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x=16?25) 0 - ns t d(clkh-noel) fsmc_clk high to fsmc_noe low - 1 ns t d(clkl-noeh) fsmc_clk low to fsmc_noe high 1 - ns t d(clkl-adv) fsmc_clk low to fsmc_ad[15:0] valid - 3 ns t d(clkl-adiv) fsmc_clk low to fsmc_ad[15:0] invalid 0 - ns t su(adv-clkh) fsmc_a/d[15:0] valid data before fsmc_clk high 5 -ns t h(clkh-adv) fsmc_a/d[15:0] valid data after fsmc_clk high 0 - ns
stm32f21xxx electrical characteristics doc id 17050 rev 8 129/173 figure 58. synchronous multiplexed psram write timings table 74. synchronous multiplexed psram write timings (1)(2) 1. c l = 30 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(clk) fsmc_clk period 2t hclk - 1 - ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x=0..2) - 0 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x= 0?2) 2 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 2 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 3 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x=16?25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x=16?25) 7 - ns t d(clkl-nwel) fsmc_clk low to fsmc_nwe low - 1 ns t d(clkl-nweh) fsmc_clk low to fsmc_nwe high 0 - ns t d(clkl-adiv) fsmc_clk low to fsmc_ad[15:0] invalid 0 - ns t d(clkl-data ) fsmc_a/d[15:0] valid data after fsmc_clk low - 2 ns t d(clkl-nblh) fsmc_clk low to fsmc_nbl high 0.5 - ns fsmc_clk fsmc_nex fsmc_nadv fsmc_a[25:16] fsmc_nwe fsmc_ad[15:0] ad[15:0] d1 d2 fsmc_nwait (waitcfg = 0b, waitpol + 0b) t w(clk) t w(clk) data latency = 0 busturn = 0 t d(clkl-nexl) t d(clkl-nexh) t d(clkl-nadvl) t d(clkl-av) t d(clkl-nadvh) t d(clkl-aiv) t d(clkl-nweh) t d(clkl-nwel) t d(clkl-nblh) t d(clkl-adv) t d(clkl-adiv) t d(clkl-data) t su(nwaitv-clkh) t h(clkh-nwaitv) ai14992g t d(clkl-data) fsmc_nbl
electrical characteristics stm32f21xxx 130/173 doc id 17050 rev 8 figure 59. synchronous non-multiplexed nor/psram read timings table 75. synchronous non-multiplexed nor/psram read timings (1)(2) 1. c l = 30 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(clk) fsmc_clk period 2t hclk -ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x=0..2) - 0 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x= 0?2) 1 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 2.5 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 4 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x=16?25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x=16?25) 3 - ns t d(clkh-noel) fsmc_clk high to fsmc_noe low - 1 ns t d(clkl-noeh) fsmc_clk low to fsmc_noe high 1.5 - ns t su(dv-clkh) fsmc_d[15:0] valid data before fsmc_clk high 8 - ns t h(clkh-dv) fsmc_d[15:0] valid data af ter fsmc_clk high 3.5 - ns fsmc_clk fsmc_nex fsmc_a[25:0] fsmc_noe fsmc_d[15:0] d1 d2 fsmc_nwait (waitcfg = 1b, waitpol + 0b) fsmc_nwait (waitcfg = 0b, waitpol + 0b) t w(clk) t w(clk) data latency = 0 busturn = 0 t d(clkl-nexl) t d(clkl-nexh) t d(clkl-av) t d(clkl-aiv) t d(clkh-noel) t d(clkl-noeh) t su(dv-clkh) t h(clkh-dv) t su(dv-clkh) t h(clkh-dv) t su(nwaitv-clkh) t h(clkh-nwaitv) t su(nwaitv-clkh) t h(clkh-nwaitv) t su(nwaitv-clkh) t h(clkh-nwaitv) ai14894g fsmc_nadv t d(clkl-nadvl) t d(clkl-nadvh)
stm32f21xxx electrical characteristics doc id 17050 rev 8 131/173 figure 60. synchronous non-multiplexed psram write timings table 76. synchronous non-multiplexed psram write timings (1)(2) 1. c l = 30 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(clk) fsmc_clk period 2t hclk - 1 - ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x=0..2) - 1 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x= 0?2) 1 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 5 ns t d(clkl- nadvh) fsmc_clk low to fsmc_nadv high 6 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x=16?25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x=16?25) 8 - ns t d(clkl-nwel) fsmc_clk low to fsmc_nwe low - 1 ns t d(clkl-nweh) fsmc_clk low to fsmc_nwe high 1 - ns t d(clkl-data) fsmc_d[15:0] valid data after fsmc_clk low - 2 ns t d(clkl-nblh) fsmc_clk low to fsmc_nbl high 2 - ns fsmc_clk fsmc_nex fsmc_a[25:0] fsmc_nwe fsmc_d[15:0] d1 d2 fsmc_nwait (waitcfg = 0b, waitpol + 0b) t w(clk) t w(clk) data latency = 0 busturn = 0 t d(clkl-nexl) t d(clkl-nexh) t d(clkl-av) t d(clkl-aiv) t d(clkl-nweh) t d(clkl-nwel) t d(clkl-data) t su(nwaitv-clkh) t h(clkh-nwaitv) ai14993g fsmc_nadv t d(clkl-nadvl) t d(clkl-nadvh) t d(clkl-data) fsmc_nbl t d(clkl-nblh)
electrical characteristics stm32f21xxx 132/173 doc id 17050 rev 8 pc card/compactflash controller waveforms and timings figure 61 through figure 66 represent synchronous waveforms together with ta bl e 77 and ta bl e 78 provides the corresponding timings. the results shown in this table are obtained with the following fsmc configuration: com.fsmc_setuptime = 0x04; com.fsmc_waitsetuptime = 0x07; com.fsmc_holdsetuptime = 0x04; com.fsmc_hizsetuptime = 0x00; att.fsmc_setuptime = 0x04; att.fsmc_waitsetuptime = 0x07; att.fsmc_holdsetuptime = 0x04; att.fsmc_hizsetuptime = 0x00; io.fsmc_setuptime = 0x04; io.fsmc_waitsetuptime = 0x07; io.fsmc_holdsetuptime = 0x04; io.fsmc_hizsetuptime = 0x00; tclrsetuptime = 0; tarsetuptime = 0; in all timing tables, the t hclk is the hclk clock period. figure 61. pc card/compactflash controller waveforms for common memory read access 1. fsmc_nce4_2 remains high (inactive during 8-bit access. fsmc_nwe t w(noe) fsmc_n oe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_2 (1) fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nce4_1-noe) t su(d-noe) t h(noe-d) t v(ncex-a) t d(nreg-ncex) t d(niord-ncex) t h(ncex-ai) t h(ncex-nreg) t h(ncex-niord) t h(ncex- niowr ) ai14895b
stm32f21xxx electrical characteristics doc id 17050 rev 8 133/173 figure 62. pc card/compactflash controller waveforms for common memory write access t d(nce4_1-nwe) t w(nwe) t h(nwe-d) t v(nce4_1-a) t d(nreg-nce4_1) t d(niord-nce4_1) t h(nce4_1-ai) memxhiz =1 t v(nwe-d) t h(nce4_1-nreg) t h(nce4_1-niord) t h(nce4_1-niowr) ai14896b fsmc_nwe fsmc_n oe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nwe-nce4_1) t d(d-nwe) fsmc_nce4_2 high
electrical characteristics stm32f21xxx 134/173 doc id 17050 rev 8 figure 63. pc card/compactflash controller waveforms for attribute memory read access 1. only data bits 0...7 are read (bits 8...15 are disregarded). t d(nce4_1-noe) t w(noe) t su(d-noe) t h(noe-d) t v(nce4_1-a) t h(nce4_1-ai) t d(nreg-nce4_1) t h(nce4_1-nreg) ai14897b fsmc_nwe fsmc_noe fsmc_d[15:0] (1) fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(noe-nce4_1) high
stm32f21xxx electrical characteristics doc id 17050 rev 8 135/173 figure 64. pc card/compactflash controller waveforms for attribute memory write access 1. only data bits 0...7 are driven (bits 8...15 remains hi-z). figure 65. pc card/compactflash controller waveforms for i/o space read access t w(nwe) t v(nce4_1-a) t d(nreg-nce4_1) t h(nce4_1-ai) t h(nce4_1-nreg) t v(nwe-d) ai14898b fsmc_nwe fsmc_noe fsmc_d[7:0](1) fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nwe-nce4_1) high t d(nce4_1-nwe) t d(niord-nce4_1) t w(niord) t su(d-niord) t d(niord-d) t v(ncex-a) t h(nce4_1-ai) ai14899b fsmc_nwe fsmc_noe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord
electrical characteristics stm32f21xxx 136/173 doc id 17050 rev 8 figure 66. pc card/compactflash controller waveforms for i/o space write access t d(nce4_1-niowr) t w(niowr) t v(ncex-a) t h(nce4_1-ai) t h(niowr-d) attxhiz =1 t v(niowr-d) ai14900c fsmc_nwe fsmc_noe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord table 77. switching characteristics for pc card/cf read and write cycles in attribute/common space (1)(2) symbol parameter min max unit t v(ncex-a) fsmc_ncex low to fsmc_ay valid - 0 ns t h(ncex_ai) fsmc_ncex high to fsmc_ax invalid 4 - ns t d(nreg-ncex) fsmc_ncex low to fsmc_nreg valid - 3.5 ns t h(ncex-nreg) fsmc_ncex high to fsmc_nreg invalid t hclk + 4 - ns t d(ncex-nwe) fsmc_ncex low to fsmc_nwe low - 5t hclk + 1 ns t d(ncex-noe) fsmc_ncex low to fsmc_noe low - 5t hclk ns t w(noe) fsmc_noe low width 8t hclk ? 0.5 8t hclk + 1 ns t d(noe_ncex) fsmc_noe high to fsmc_ncex high 5t hclk + 2.5 - ns t su (d-noe) fsmc_d[15:0] valid data before fsmc_noe high 4 - ns t h (n0e-d) fsmc_n0e high to fsmc_d[15:0] invalid 2 - ns t w(nwe) fsmc_nwe low width 8t hclk - 1 8t hclk + 4 ns t d(nwe_ncex ) fsmc_nwe high to fsmc_ncex high 5t hclk + 1.5 ns t d(ncex-nwe) fsmc_ncex low to fsmc_nwe low - 5hclk+ 1 ns t v (nwe-d) fsmc_nwe low to fsmc_d[15:0] valid - 0 ns t h (nwe-d) fsmc_nwe high to fsmc_d[15:0] invalid 8 t hclk -ns t d (d-nwe) fsmc_d[15:0] valid before fsmc_nwe high 13t hclk -ns 1. c l = 30 pf. 2. based on characterization, not tested in production.
stm32f21xxx electrical characteristics doc id 17050 rev 8 137/173 nand controller waveforms and timings figure 67 through figure 70 represent synchronous waveforms, together with ta b l e 79 and ta bl e 80 provides the corresponding timings. the results shown in this table are obtained with the following fsmc configuration: com.fsmc_setuptime = 0x01; com.fsmc_waitsetuptime = 0x03; com.fsmc_holdsetuptime = 0x02; com.fsmc_hizsetuptime = 0x01; att.fsmc_setuptime = 0x01; att.fsmc_waitsetuptime = 0x03; att.fsmc_holdsetuptime = 0x02; att.fsmc_hizsetuptime = 0x01; bank = fsmc_bank_nand; memorydatawidth = fsmc_memorydatawidth_16b; ecc = fsmc_ecc_enable; eccpagesize = fsmc_eccpagesize_512bytes; tclrsetuptime = 0; tarsetuptime = 0; in all timing tables, the t hclk is the hclk clock period. table 78. switching characteristics for pc card/cf read and write cycles in i/o space (1)(2) symbol parameter min max unit t w(niowr) fsmc_niowr low width 8t hclk - 0.5 - ns t v(niowr-d) fsmc_niowr low to fsmc_d[15:0] valid - 5t hclk - 1 ns t h(niowr-d) fsmc_niowr high to fsmc_d[15:0] invalid 8t hclk - 3 - ns t d(nce4_1-niowr) fsmc_nce4_1 low to fsmc_niowr valid - 5t hclk + 1.5 ns t h(ncex-niowr) fsmc_ncex high to fsmc_niowr invalid 5t hclk -ns t d(niord-ncex) fsmc_ncex low to fsmc_niord valid - 5t hclk + 1 ns t h(ncex-niord) fsmc_ncex high to fsmc_niord) valid 5t hclk ? 0.5 - ns t w(niord) fsmc_niord low width 8t hclk + 1 - ns t su(d-niord) fsmc_d[15:0] valid before fsmc_niord high 9.5 ns t d(niord-d) fsmc_d[15:0] valid after fsmc_niord high 0 ns 1. c l = 30 pf. 2. based on characterization, not tested in production.
electrical characteristics stm32f21xxx 138/173 doc id 17050 rev 8 figure 67. nand controller waveforms for read access figure 68. nand controller waveforms for write access fsmc_nwe fsmc_noe (nre) fsmc_d[15:0] t su(d-noe) t h(noe-d) ai14901c ale (fsmc_a17) cle (fsmc_a16) fsmc_ncex t d(ale-noe) t h(noe-ale) t h(nwe-d) t v(nwe-d) ai14902c fsmc_nwe fsmc_noe (nre) fsmc_d[15:0] ale (fsmc_a17) cle (fsmc_a16) fsmc_ncex t d(ale-nwe) t h(nwe-ale)
stm32f21xxx electrical characteristics doc id 17050 rev 8 139/173 figure 69. nand controller waveforms for common memo ry read access figure 70. nand controller waveforms for common memory write access table 79. switching characteristics for nand flash read cycles (1)(2) 1. c l = 30 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(n0e) fsmc_noe low width 4t hclk - 1 4t hclk + 2 ns t su(d-noe) fsmc_d[15-0] valid data before fsmc_noe high 9-ns t h(noe-d ) fsmc_d[15-0] valid data after fsmc_noe high 3 - ns t d(ale-noe) fsmc_ale valid before fsmc_noe low - 3t hclk ns t h(noe-ale) fsmc_nwe high to fsmc_ale invalid 3t hclk + 2 - ns fsmc_nwe fsmc_n oe fsmc_d[15:0] t w(noe) t su(d-noe) t h(noe-d) ai14912c ale (fsmc_a17) cle (fsmc_a16) fsmc_ncex t d(ale-noe) t h(noe-ale) t w(nwe) t h(nwe-d) t v(nwe-d) ai14913c fsmc_nwe fsmc_n oe fsmc_d[15:0] t d(d-nwe) ale (fsmc_a17) cle (fsmc_a16) fsmc_ncex t d(ale-noe) t h(noe-ale)
electrical characteristics stm32f21xxx 140/173 doc id 17050 rev 8 5.3.26 camera interface (dcmi) timing specifications 5.3.27 sd/sdio mmc ca rd host interface (sdio) characteristics unless otherwise specified, the parameters given in ta bl e 82 are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in ta b l e 11 . refer to section 5.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (d[7:0], cmd, ck). figure 71. sdio high-speed mode table 80. switching characterist ics for nand flash write cycles (1)(2) 1. c l = 30 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(nwe) fsmc_nwe low width 4t hclk - 1 4t hclk + 3 ns t v(nwe-d) fsmc_nwe low to fsmc_d[15-0] valid - 0 ns t h(nwe-d) fsmc_nwe high to fsmc_d[15-0] invalid 3t hclk -ns t d(d-nwe) fsmc_d[15-0] valid before fsmc_nwe high 5t hclk -ns t d(ale-nwe) fsmc_ale valid before fsmc_nwe low - 3t hclk + 2 ns t h(nwe-ale) fsmc_nwe high to fsmc_ale invalid 3t hclk - 2 - ns table 81. dcmi characteristics symbol parameter conditions min max frequency ratio dcmi_pixclk/ f hclk dcmi_pixclk= 48 mhz 0.4 t w(ckh) ck d, cmd (output) d, cmd (input) t c t w(ckl) t ov t oh t isu t ih t f t r ai14887
stm32f21xxx electrical characteristics doc id 17050 rev 8 141/173 figure 72. sd default mode 5.3.28 rtc characteristics table 82. sd / mmc characteristics symbol parameter conditions min max unit f pp clock frequency in data transfer mode c l 30 pf 0 48 mhz - sdio_ck/f pclk2 frequency ratio - - 8/3 - t w(ckl) clock low time, f pp = 16 mhz c l 30 pf 32 ns t w(ckh) clock high time, f pp = 16 mhz c l 30 pf 31 t r clock rise time c l 30 pf 3.5 t f clock fall time c l 30 pf 5 cmd, d inputs (referenced to ck) t isu input setup time c l 30 pf 2 ns t ih input hold time c l 30 pf 0 cmd, d outputs (referenced to ck) in mmc and sd hs mode t ov output valid time c l 30 pf 6 ns t oh output hold time c l 30 pf 0.3 cmd, d outputs (referenced to ck) in sd default mode (1) 1. refer to sdio_clkcr, the sdi clock control register to control the ck output. t ovd output valid default time c l 30 pf 7 ns t ohd output hold default time c l 30 pf 0.5 ai14888 ck d, cmd (output) t ovd t ohd table 83. rtc characteristics symbol parameter conditions min max -f pclk1 /rtcclk frequency ratio any read/write operation from/to an rtc register 4-
package characteristics stm32f21xxx 142/173 doc id 17050 rev 8 6 package characteristics 6.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
stm32f21xxx package characteristics doc id 17050 rev 8 143/173 figure 73. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline 1. drawing is not to scale. a a2 a1 c l1 l e e1 d d1 e b ai14398b table 84. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 12.000 0.4724 d1 10.000 0.3937 e 12.000 0.4724 e1 10.000 0.3937 e 0.500 0.0197 0 3.5 7 0 3.5 7 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 n number of pins 64 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f21xxx 144/173 doc id 17050 rev 8 figure 74. recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. figure 75. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline 1. drawing is not to scale. 48 32 49 64 17 116 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909 d d1 d3 75 51 50 76 100 26 125 e3 e1 e e b pin 1 identification seating plane gage plane c a a2 a1 c ccc 0.25 mm 0.10 inch l l1 k c 1l_me
stm32f21xxx package characteristics doc id 17050 rev 8 145/173 figure 76. recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. table 85. lqpf100 ? 14 x 14 mm 100-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 12.000 0.4724 e 15.80v 16.000 16.200 0.6220 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 12.000 0.4724 e 0.500 0.0197 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 03.57 03.57 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. 75 51 50 76 0.5 0.3 16.7 14.3 100 26 12.3 25 1.2 16.7 1 ai14906
package characteristics stm32f21xxx 146/173 doc id 17050 rev 8 figure 77. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline 1. drawing is not to scale. d1 d3 d e1 e3 e e pin 1 identification 73 72 37 36 109 144 108 1 aa2a1 b c a1 l l1 k seating plane c ccc c 0.25 mm gage plane me_1a table 86. lqfp144 20 x 20 mm, 144-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 21.800 22.000 22.200 0.8583 0.8661 0.874 d1 19.800 20.000 20.200 0.7795 0.7874 0.7953 d3 17.500 0.689 e 21.800 22.000 22.200 0.8583 0.8661 0.8740 e1 19.800 20.000 20.200 0.7795 0.7874 0.7953 e3 17.500 0.6890 e 0.500 0.0197 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 03.57 03.57 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
stm32f21xxx package characteristics doc id 17050 rev 8 147/173 figure 78. recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. 0.5 0.35 19.9 17.85 22.6 1.35 22.6 19.9 ai14905c 1 36 37 72 73 108 109 144
package characteristics stm32f21xxx 148/173 doc id 17050 rev 8 figure 79. lqfp176 - low profile quad flat package 24 24 1.4 mm, package outline 1. drawing is not to scale. ccc c s e a ting pl a ne c aa2 a1 c 0.25 mm g au ge pl a ne hd d a1 l l1 k 8 9 88 ehe 45 44 e 1 176 pin 1 identific a tion b 1 33 1 3 2 1t_me zd ze table 87. lqfp176 - low profile quad flat package 24 24 1.4 mm package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.450 0.0531 0.0571 b 0.170 0.270 0.0067 0.0106 c 0.090 0.200 0.0035 0.0079 d 23.900 24.100 0.9409 0.9488 e 23.900 24.100 0.9409 0.9488 e 0.500 0.0197 hd 25.900 26.100 1.0197 1.0276 he 25.900 26.100 1.0197 1.0276 l (2) 0.450 0.750 0.0177 0.0295 l1 1.000 0.0394 zd 1.250 0.0492 ze 1.250 0.0492 k0 70 7 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. 2. l dimension is measured at gauge plane at 0.25 mm above the seating plane.
stm32f21xxx package characteristics doc id 17050 rev 8 149/173 figure 80. lqfp176 recommended footprint 1. dimensions are expr essed in millimeters. 1t_fp_v1 133 132 1.2 0.3 0.5 89 88 1.2 44 45 21.8 26.7 1 176 26.7 21.8
package characteristics stm32f21xxx 150/173 doc id 17050 rev 8 figure 81. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm, package outline 1. drawing is not to scale. seating plane c a2 a4 a3 c ddd a1 a e f f e r a0e7_me_v2 a 15 1 bottom view ball a1 d e ball a1 top view table 88. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm mechanical data symbol millimeters inches (1) min typ max min typ max a 0.460 0.530 0.600 0.0181 0.0209 0.0236 a1 0.050 0.080 0.110 0.002 0.0031 0.0043 a2 0.400 0.450 0.500 0. 0157 0.0177 0.0197 a3 0.130 0.0051 a4 0.270 0.320 0.370 0. 0106 0.0126 0.0146 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 d 9.950 10.000 10.050 0.3740 0.3937 0.3957 e 9.950 10.000 10.050 0.3740 0.3937 0.3957 e 0.600 0.650 0.700 0.0236 0.0256 0.0276 f 0.400 0.450 0.500 0.0157 0.0177 0.0197 ddd 0.080 0.0031 eee 0.150 0.0059 fff 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
stm32f21xxx package characteristics doc id 17050 rev 8 151/173 6.2 thermal characteristics the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: t a max is the maximum ambient temperature in c, ja is the package junction-to-ambient thermal resistance, in c/w, p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). ava ilable from www.jedec.org. table 89. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp 64 - 10 10 mm / 0.5 mm pitch 45 c/w thermal resistance junction-ambient lqfp100 - 14 14 mm / 0.5 mm pitch 46 thermal resistance junction-ambient lqfp144 - 20 20 mm / 0.5 mm pitch 40 thermal resistance junction-ambient lqfp176 - 24 24 mm / 0.5 mm pitch 38 thermal resistance junction-ambient ufbga176 - 10 10 mm / 0.5 mm pitch 39
part numbering stm32f21xxx 152/173 doc id 17050 rev 8 7 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 90. ordering information scheme example: stm32 f 215 r e t 6 v xxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 215 = stm32f21x, connectivity, cryptographic acceleration 217= stm32f21x, connectivity, camera interface, cryptographic acceleration, ethernet pin count r = 64 pins v = 100 pins z = 144 pins i = 176 pins flash memory size e = 512 kbytes of flash memory g = 1024 kbytes of flash memory package t = lqfp h = ufbga temperature range 6 = industrial temperature range, ?40 to 85 c. 7 = industrial temperature range, ?40 to 105 c. software option internal code or blank options xxx = programmed parts tr = tape and reel
stm32f21xxx application block diagrams doc id 17050 rev 8 153/173 appendix a application block diagrams a.1 main applications versus package ta bl e 91 gives examples of configurations for each package. table 91. main applications versus package for stm32f2xxx microcontrollers 64 pins (1) 100 pins 144 pins 176 pins config 1 config 2 config 3 config 1 config 2 config 3 config 4 config 1 config 2 config 3 config 4 config 1 config 2 usb otg fs otg fs - - -xxx-x-x-x- fs - - - xxxxxxxxx - usb otg hs hs ulpi x - xx - - - xx - - xx otg fs xxxx - - - xx - - xx fs xxxxxxxxxxxxx ethernet (2) mii -----xx-- xxxx rmii---- xxxxxxxxx spi/i2s2 spi/i2s3 - x - - xxxxxxxxx sdio sdio x x - sdio or dcmi sdio or dcmi sdio or dcmi x sdio or dcmi x sdio or dcmi xxx dcmi (2) 8-bit data --- x x xxx 10-bit data --- x x xxx 12-bit data --- x x xxx 14-bit data --------x-xxx fsmc nor/ ram muxed - - - xxxxxxxxxx nor/ ram - - - xxxxxx nand- - - xxx xxxxxxx cf ------- xxxxxx can - xx - xxx - - xx - x 1. not available on stm32f2x7xx. 2. not available on stm32f2x5xx.
application block diagrams stm32f21xxx 154/173 doc id 17050 rev 8 a.2 application exampl e with regulator off figure 82. regulator off/internal reset on 1. this mode is available only on ufbga176. 2. in regulator bypass mode, pa0 is used as power-on reset. the connection between pa0 and nrst can consequently prevent debug connection. if the debug connec tion under reset or pre-reset is requi red, the user must manage the reset and the power-on reset separately. a.3 usb otg full speed (fs) interface solutions figure 83. usb otg fs (full speed) device-only connection 1. the same application can be developed using the otg hs in fs mode to achieve enhanced performance thanks to the large rx/tx fifo and to a dedicated dma controller. regoff vcap_1 ai18476 vcap_2 pa0 nrst application reset signal (optional) 1.2 v v dd (1.8 to 3.6 v) power-down reset risen after vcap_1/vcap_2 stabilization regoff vcap_1 vcap_2 pa0 1.2 v v dd (1.8 to 3.6 v) power-down reset risen before vcap_1/vcap_2 stabilization nrst irroff vdd vdd application reset signal (optional) v cap_1/2 monitoring ext. reset controller active when v cap_1/2 < 1.08 v stm32f20xxx 5v to v dd volatge regulator (1) v dd vbus dp v ss pa9 pa12 pa11 usb std-b connector dm osc_in osc_out ai17295
stm32f21xxx application block diagrams doc id 17050 rev 8 155/173 figure 84. usb otg fs (full speed) host-only connection 1. the current limiter is required onl y if the application has to support a v bus powered device. a basic power switch can be used if 5 v are available on the application board. 2. the same application can be developed using the otg hs in fs mode to achieve enhanced performance thanks to the large rx/tx fifo and to a dedicated dma controller. figure 85. otg fs (full speed) connection dual-role with internal phy 1. external voltage regulator only needed when building a v bus powered device. 2. the current limiter is required onl y if the application has to support a v bus powered device. a basic power switch can be used if 5 v are available on the application board. 3. the id pin is required in dual role only. 4. the same application can be developed using the otg hs in fs mode to achieve enhanced performance thanks to the large rx/tx fifo and to a dedicated dma controller. stm32f20xx v dd vbus dp v ss pa 9 pa 1 2 pa 1 1 usb std-a connector dm gpio+irq gpio en overcurrent 5 v pwr osc_in osc_out ai17296c current limiter power switch (1) stm32f20xxx v dd vbus dp v ss pa9 pa1 2 pa1 1 usb micro-ab connector dm gpio+irq gpio en overcurrent 5 v pwr 5 v to v dd voltage regulator (1) v dd i d (3) pa1 0 osc_in osc_out ai17294c current limiter power switch (2)
application block diagrams stm32f21xxx 156/173 doc id 17050 rev 8 a.4 usb otg high speed (hs) interface solutions figure 86. otg hs (high speed) de vice connection, host and dual-role in high-speed mode with external phy 1. it is possible to use mco1 or mco2 to save a crys tal. it is however not mandato ry to clock the stm32f21x with a 24 or 26 mhz crystal when using usb hs. the above figure only shows an example of a possible connection. 2. the id pin is required in dual role only. dp stm32f20xxx dm v bus v ss dm dp id (2) usb usb hs otg ctrl fs phy ulpi high speed otg phy ulpi_clk ulpi_d[7:0] ulpi_dir ulpi_stp ulpi_nxt not connected connector mco1 or mco2 24 or 26 mhz xt (1) pll xt1 xi ai16036c
stm32f21xxx application block diagrams doc id 17050 rev 8 157/173 a.5 complete audio player solutions two solutions are offe red, illustrated in figure 87 and figure 88 . figure 87 shows storage media to audio dac/amplifier streaming using a software codec. this solution implements an audio crystal to provide audio class i 2 s accuracy on the master clock (0.5% error maximum, see the serial peripheral interface section in the reference manual for details). figure 87. complete audio player solution 1 figure 88 shows storage media to audio codec/amplifier streaming with sof synchronization of input/output audio streaming using a hardware codec. figure 88. complete audio player solution 2 1. sof = start of frame. cortex-m3 core up to 120 mhz otg (host mode) + phy spi/ fsmc spi gpio i2s xtal 25 mhz or 14.7456 mhz usb mass-storage device mmc/ sdcard lcd touch screen control buttons dac + audio ampli file system program memory audio codec user application ai16039c cortex-m3 core up to 120 mhz otg + phy spi/ fsmc spi/ fsmc gpio i2s usb mass-storage device mmc/ sdcard lcd touch screen control buttons audio ampli file system program memory audio pll +dac user application ai16040c sof sof synchronization of input/output audio streaming xtal 25 mhz or 14.7456 mhz
application block diagrams stm32f21xxx 158/173 doc id 17050 rev 8 figure 89. audio player solution using pll, plli2s, usb and 1 crystal figure 90. audio pll (plli2s) providing accurate i2s clock otg 48 mhz phy xtal 25 mhz or 14.7456 mhz ai18412b i2s <0.04% accuracy) dac + audio ampli mclk out sclk mco1/ mco2 plli2s x n2 pll x n1 osc div by m div by p div by q up to 120 mhz cortex-m3 core up to 120 mhz div by r mclk in mco1pre mco2pre i2 s ctl i2 s _mck = 256 f s audio 11.2 8 96 mhz for 44.1 khz 12.2 88 0 mhz for 4 8 .0 khz i2 s _mck plli2 s /m m=1,2, 3 ,..,64 1 mhz 192 to 4 3 2 mhz n=192,194,..,4 3 2 i2 s com_ck ph as ec vco /n /r clkin ph as e lock detector r=2, 3 ,4,5,6,7 i2 s d=2, 3 ,4.. 129 a i16041 b
stm32f21xxx application block diagrams doc id 17050 rev 8 159/173 figure 91. master clock (mck) used to drive the external audio dac 1. i2s_sck is the i2s serial clock to the exter nal audio dac (not to be confused with i2s_ck). figure 92. master clock (mck) not used to drive the external audio dac 1. i2s_sck is the i2s serial clock to the exter nal audio dac (not to be confused with i2s_ck). i2 s _ck i2 s controller i2 s _mck = 256 f s audio = 11.2 8 96 mhz for f s audio = 44.1 khz = 12.2 88 0 mhz for f s audio = 4 8 .0 khz /(2 x 16) / 8 /i2 s d f s audio i2 s _ s ck (1) = i2 s _mck/ 8 for 16- b it s tereo for 16- b it s tereo /(2 x 3 2) /4 for 3 2- b it s tereo f s audio 2, 3 ,4,..,129 = i2 s _mck/4 for 3 2- b it s tereo a i16042 i2 s com_ck i2 s controller /(2 x 16) /i2 s d f s audio i2 s _ s ck (1) for 16- b it s tereo /(2 x 3 2) for 3 2- b it s tereo f s audio a i16042
application block diagrams stm32f21xxx 160/173 doc id 17050 rev 8 a.6 ethernet interface solutions figure 93. mii mode using a 25 mhz crystal 1. f hclk must be greater than 25 mhz. 2. pulse per second when using ieee1588 ptp optional signal. figure 94. rmii with a 50 mhz oscillator 1. f hclk must be greater than 25 mhz. mcu ethernet mac 10/100 ethernet phy 10/100 pll hclk xt1 phy_clk 25 mhz mii_rx_clk mii_rxd[3:0] mii_rx_dv mii_rx_er mii_tx_clk mii_tx_en mii_txd[3:0] mii_crs mii_col mdio mdc hclk (1) pps_out (2) xtal 25 mhz stm32 osc tim2 timestamp comparator timer input trigger ieee1588 ptp mii = 15 pins mii + mdc = 17 pins ms19968v1 mco1/mco2 mcu ethernet mac 10/100 ethernet phy 10/100 pll hclk xt1 50mhz rmii_rxd[1:0] rmii_crx_dv rmii_ref_clk rmii_tx_en rmii_txd[1:0] mdio mdc hclk (1) stm32 osc 50 mhz tim2 timestamp comparator timer input trigger ieee1588 ptp rmii = 7 pins rmii + mdc = 9 pins ms19971v1 /2 or /20 synchronous 2.5 or 25 mhz 50 mhz 50 mhz xtal osc
stm32f21xxx application block diagrams doc id 17050 rev 8 161/173 figure 95. rmii with a 25 mhz crystal and phy with pll 1. f hclk must be greater than 25 mhz. 2. the 25 mhz (phy_clk) must be derived directly from the hse oscillator , before the pll block. mcu ethernet mac 10/100 ethernet phy 10/100 pll hclk xt1 phy_clk 25 mhz rmii_rxd[1:0] rmii_crx_dv rmii_ref_clk rmii_tx_en rmii_txd[1:0] mdio mdc hclk (1) stm32f tim2 timestamp comparator timer input trigger ieee1588 ptp rmii = 7 pins rmii + mdc = 9 pins ms19970v1 /2 or /20 synchronous 2.5 or 25 mhz 50 mhz xtal 25 mhz osc pll ref_clk mco1/mc02
revision history stm32f21xxx 162/173 doc id 17050 rev 8 8 revision history table 92. document revision history date revision changes 02-feb-2010 1 initial release. 13-jul-2010 2 updated datasheet status to preliminary data. renamed high-speed sr am, system sram. added ufbga176 package, and note 1 related to lqfp176 package in ta bl e 2 , figure 11 , and ta b l e 9 0 . added information on art accelerator and audio pll (plli2s). added table 4: usart feature comparison . several updates on table 5: stm32f21x pin and ball definitions and table 7: alternate function mapping . adc, dac, oscillator, rtc_af, wkup and vbus signals removed from alternate functions and moved to the ?other functions? column in table 5: stm32f21x pin and ball definitions . traceswo added in figure 4: stm32f21x block diagram , ta b l e 5 : stm32f21x pin and ball definitions , and table 7: alternate function mapping . xtal oscillator frequency updated on cover page, in figure 4: stm32f21x block diagram and in section 2.2.11: external interrupt/event controller (exti) . updated list of peripherals used for boot mode in section 2.2.13: boot modes . added regulator bypass mode in section 2.2.16: voltage regulator , and section 5.3.4: operat ing conditions at power-up / power-down (regulator off) . updated section 2.2.17: real-time clock (rtc), backup sram and backup registers . added note note: in section 2.2.18: low-power modes . added spi ti protocol in section 2.2.23: serial peripheral interface (spi) . updated section 2.2.28: universal serial bus on-the-go full-speed (otg_fs) , and section 2.2.29: universal serial bus on-the-go high- speed (otg_hs) . added section 5: electrical characteristics , and section 6.2: thermal characteristics . updated table 87: lqfp176 - low profile quad flat package 24 24 1.4 mm package mechanical data and figure 79: lqfp176 - low profile quad flat package 24 24 1.4 mm, package outline . added table 91: main applications versus package for stm32f2xxx microcontrollers in a.1: main applications versus package . updated figures in appendix a.3: usb otg full speed (fs) interface solutions and a.4: usb otg high speed (hs) interface solutions . updated figure 89: audio player solution using pll, plli2s, usb and 1 crystal and figure 90: audio pll (plli2s) providing accurate i2s clock . added random number generation feature. added trademark for art accelerator and updated section 2.2.2: adaptive real-time memory accelerator (art accelerator?) .
stm32f21xxx revision history doc id 17050 rev 8 163/173 25-nov-2010 3 added wlcsp66 (64+2) package. added note 1 related to lqfp176 on cover page. update i/os in section : features . updated table 5: multi-ahb matrix . added case of bor inactivation using irroff on wlcsp devices in section 2.2.15: power supply supervisor . reworked section 2.2.16: voltage regulator to clarify regulator off modes. added section 2.2.19: vbat operation . modified v dd_3 pin in table 5: stm32f21x pin and ball definitions , and added note related to the fsmc_nl pin. renamed bypass-reg regoff, and add irroff pin. changed v ss_sa to v ss , and v dd_sa pin reserved for future use. updated maximum hse crystal frequency to 26 mhz. usart4/5 renamed uart4/5. usart4 pins renamed uart4 in table 5: stm32f21x pin and ball definitions . updated lin and irda features for uart4/5 in table 4: usart feature comparison . section 5.2: absolu te maximum ratings : updated v in minimum and maximum values and note for non-five-volt tolerant pins in table 8: voltage characteristics . updated i inj(pin) maximum values and related notes in table 9: current characteristics . updated v dda minimum value in table 11: general operating conditions . added note 2 and updated maximum cpu frequency in table 12: limitations depending on the operating power supply range ; and added figure 18: number of wait states versus fcpu and vdd range . renamed brownout low, medium and high reset thresholds, renamed v borl /v borm /v borh , v bor1 /v bor2 /v bor3 in table 16: embedded reset and power control block characteristics . changed f lsi typical value in table 30: lsi oscillator characteristics . added figure 32: acclsi versus temperature . changed f osc_in maximum value in table 27: hse 4-26 mhz oscillator characteristics . changed f pll_in maximum value in table 31: main pll characteristics , and updated jitter parameters in table 32: plli2s (audio pll) characteristics . section 5.3.16: i/o port characteristics : updated v ih and v il in table 43: i/o static characteristics . added note 1 below table 44: output voltage characteristics . updated r pd and r pu parameter description in table 54: usb otg fs dc electrical characteristics . updated v ref+ minimum value in table 63: adc characteristics . updated table 68: embedded internal reference voltage . removed ethernet and usb2 for 64-pin devices in ta b l e 9 1 : m a i n applications versus package for stm32f2xxx microcontrollers . added a.2: application example with regulator off , removed ?otg fs connection with external phy? figure, updated figure 84 , figure 85 , and figure 87 to add stulpi01b. table 92. document revision history (continued) date revision changes
revision history stm32f21xxx 164/173 doc id 17050 rev 8 22-apr-2011 4 changed datasheet status to ?full datasheet?. apb1 frequency changed form 36 mhz to 30 mhz. introduced concept of sram1 and sram2. lqfp176 now in production. removed wlcsp64+2 package. updated figure 3: compatible board design between stm32f10xx and stm32f2xx for lqfp144 package and figure 2: compatible board design between stm32f10 xx and stm32f2xx for lqfp100 package . added camera interface for stm32f217vx devices in ta b l e 2 : stm32f215xx and stm32f217xx: f eatures and peripheral counts . removed 16 mhz internal rc oscillator accuracy in section 2.2.12: clocks and startup . updated section 2.2.16: voltage regulator . modified i 2 s sampling frequency range in section 2.2.12: clocks and startup , section 2.2.24: inter-in tegrated sound (i2s) , and section 2.2.30: audio pll (plli2s) . updated section 2.2.17: real-time clock (rtc), backup sram and backup registers and description of tim2 and tim5 in section : general-purpose timers (timx) . modified maximum baud rate (oversampling by 16) for usart1 in table 4: usart feature comparison . updated note related to rfu pin below figure 9: stm32f21x lqfp100 pinout , figure 10: stm32f21x lqfp144 pinout , figure 11: stm32f21x lqfp176 pinout , figure 12: stm32f21x ufbga176 ballout , and table 5: stm32f21x pin and ball definitions . added rtc_50hz as pb15 alternate function, and tt (3.6 v tolerant i/o) in table 5: stm32f21x pin and ball definitions and ta bl e 7 : alternate function mapping . pa15 added in table 5: stm32f21x pin and ball definitions . in table 5: stm32f21x pin and ball definitions , changed i2s2_ck and i2s3_ck to i2s2_sck and i2s3_sck, respectively. removed eth _rmii_tx_clk for pc3/af11 in table 7: alternate function mapping . updated table 8: voltage characteristics and table 9: current characteristics . t stg updated to ?65 to +150 in table 10: thermal characteristics . added cext and esr in table 11: general operating conditions as well as section 5.3.2: vcap1/vcap2 external capacitor . modified note 3 in table 12: limitations depending on the operating power supply range . updated table 14: operating conditions at power-up / power-down (regulator on) , and table 15: operating conditions at power-up / power-down (regulator off) . updated notes below and added osc_out pin in figure 14: pin loading conditions . and figure 15: pin input voltage . updated v pvd , v bor1 , v bor2 , v bor3 , t rsttempo typical value, and i rush , added e rush and note 3 in table 16: embedded reset and power control block characteristics . table 92. document revision history (continued) date revision changes
stm32f21xxx revision history doc id 17050 rev 8 165/173 22-apr-2011 4 (continued) updated typical and maximum current consumption conditions, as well as table 17: typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator disabled) and table 18: typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabled) or ram . added figure 20 , figure 21 , figure 22 , and figure 23 . updated table 19: typical and maximum current consumption in sleep mode , and added figure 24 and figure 25 . updated table 21: typical and maximum current consumptions in standby mode and table 22: typical and maximum current consumptions in vbat mode . updated table 20: typical and maximum current consumptions in stop mode . added figure 26: typical current consumption vs temperature in stop mode . updated table 21: typical and maximum current consumptions in standby mode and table 22: typical and maximum current consumptions in vbat mode . updated on-chip peripheral current consumption conditions and table 23: peripheral current consumption . updated t wustdby and t wustop , and added note 3 in table 24: low- power mode wakeup timings . maximum f hse_ext and minimum t w(hse) values updated in table 25: high-speed external user clock characteristics . updated c and g m in table 27: hse 4-26 mhz oscillator characteristics . updated r f , i 2 , g m , and t su(lse) in table 28: lse oscillator characteristics (flse = 32.768 khz) . added note 3 and updated acc hsi , idd (hsi) and t su(hsi) in table 29: hsi oscillator characteristics . added figure 31: acchsi versus temperature updated f lsi , t su(lsi) and idd (lsi) in table 30: lsi oscillator characteristics . table 31: main pll characteristics : removed note 1, updated t lock , jitter, idd (pll) and idd a(pll) , added note 2 for f pll_in minimum and maximum values. table 32: plli2s (audio pll) characteristics : removed note 1, updated t lock , jitter, idd (plli2s) and idd a(plli2s) , added note 2 for f plli2s_in minimum and maximum values. added note 1 in table 33: sscg parameters constraint . updated table 34: flash memory characteristics . modified table 35: flash memory programming and added note 1 for t prog . updated t prog and added note 1 in table 36: flash memory programming with vpp . modified figure 36: recommended nrst pin protection . updated table 39: emi characteristics and emi monitoring conditions in section : electromagnetic interference (emi) . added note 2 related to v esd(hbm) in table 40: esd absolute maximum ratings . added section 5.3.15: i/o current injection characteristics . updated table 43: i/o static characteristics . modified maximum frequency values and conditions in table 45: i/o ac characteristics . table 92. document revision history (continued) date revision changes
revision history stm32f21xxx 166/173 doc id 17050 rev 8 22-apr-2011 4 (continued) updated t res(tim) in table 47: characteristics of timx connected to the apb1 domain . modified t res(tim) and f ext table 48: characteristics of timx connected to the apb2 domain . changed t w(sckh) to t w(sclh) , t w(sckl) to t w(scll) , t r(sck) to t r(scl) , and t f(sck) to t f(scl) in table 49: i2c characteristics and figure 37: i2c bus ac waveforms and measurement circuit . added table 54: usb otg fs dc electrical characteristics and updated table 55: usb otg fs electrical characteristics . updated v dd minimum value in table 59: ethernet dc electrical characteristics . updated table 63: adc characteristics and r ain equation. updated r ain equation. updated table 65: dac characteristics . updated t start in table 66: ts characteristics . updated table 68: embedded internal reference voltage . modified fsmc_noe waveform in figure 53: asynchronous non- multiplexed sram/psram/nor read waveforms . shifted end of fsmc_nex/nadv/addresses/nwe/noe /nwait of a half fsmc_clk period, changed t d(clkh-nexh ) to t d(clkl-nexh) , t d(clkh-aiv) to t d(clkl- aiv) , t d(clkh-noeh) to t d(clkl-noeh) , and t d(clkh-nweh) to t d(clkl- nweh) , and updated data latency from 1 to 0 in figure 57: synchronous multiplexed nor/psram read timings , figure 58: synchronous multiplexed psram write timings , figure 59: synchronous non-multiplexed nor/psram read timings , and figure 60: synchronous non-multiplexed psram write timings , changed t d(clkh-nexh ) to t d(clkl-nexh) , t d(clkh-aiv) to t d(clkl-aiv) , t d(clkh-noeh) to t d(clkl-noeh) , t d(clkh-nweh) to t d(clkl-nweh) , and modified t w(clk) minimum value in ta b l e 7 3 , ta b l e 7 4 , table 75 , and table 76 . updated r typical value in table 67: vbat monitoring characteristics .updated note 2 in ta b l e 6 9 , table 70 , ta bl e 7 1 , table 72 , ta bl e 7 3 , table 74 , ta b l e 7 5 , and ta bl e 7 6 . modified t h(niowr-d) in figure 66: pc card/compactflash controller waveforms for i/o space write access . modified fsmc_ncex signal in figure 67: nand controller waveforms for read access , figure 68: nand controller waveforms for write access , figure 69: nand controller waveforms for common memory read access , and figure 70: nand controller waveforms for common memory write access . specified full speed (fs) mode for figure 86: usb otg hs peripheral-only connection in fs mode and figure 87: usb otg hs host-only connection in fs mode . table 92. document revision history (continued) date revision changes
stm32f21xxx revision history doc id 17050 rev 8 167/173 14-jun-2011 5 added sdio in table 2: stm32f215xx and stm32f217xx: features and peripheral counts . updated v in for 5v tolerant pins in table 8: voltage characteristics . updated jitter parameters description in table 31: main pll characteristics . remove jitter values for system clock in table 32: plli2s (audio pll) characteristics . updated table 39: emi characteristics . update note 2 in table 49: i2c characteristics . updated avg_slope typical value and t s_temp minimum value in table 66: ts characteristics . updated t s_vbat minimum value in table 67: vbat monitoring characteristics . updated t s_vrefint minimum value in table 68: embedded internal reference voltage . added software option in section 7: part numbering . in table 91: main applications versus package for stm32f2xxx microcontrollers , renamed usb1 and usb2, usb otg fs and usb otg hs, respectively; and removed usb otg fs and camera interface for 64-pin package; added usb otg hs on 64-pin package; and added note 1 and note 2 . updated disclaimer on cover page. table 92. document revision history (continued) date revision changes
revision history stm32f21xxx 168/173 doc id 17050 rev 8 20-dec-2011 6 updated sdio register addresses in figure 13: memory map . updated figure 3: compatible board design between stm32f10xx and stm32f2xx for lqfp144 package , figure 2: compatible board design between stm32f10xx and stm32f2xx for lqfp100 package , figure 1: compatible board design between stm32f10xx and stm32f2xx for lqfp64 package , and added figure 4: compatible board design between stm32f10xx and stm32f2xx for lqfp176 package . updated section 2.2.3: memo ry protection unit . updated section 2.2.6: embedded sram . updated section 2.2.28: universal serial bus on-the-go full-speed (otg_fs) to remove external fs otg phy support. in table 5: stm32f21x pin and ball definitions : changed spi2_mck and spi3_mck to i2s2_mck and i2s3_mck, respectively. added eth _rmii_tx_en alternate functi on to pg11. added eventout in the list of alternate functions for i/o pin/balls. removed otg_fs_sda, otg_fs_scl and otg_fs_intn alternate functions. in table 7: alternate function mapping : changed i2s3_sck to i2s3_mck for pc7/af6, added fsmc_nce3 for pg9, fsmc_ne3 for pg10, and fsmc_nce2 for pd7. removed otg_fs_sda, otg_fs_scl and otg_fs_intn alternate functions. updated peripherals corresponding to af12. removed cext and esr from table 11: general operating conditions . added maximum power consumption at t a =25 c in table 20: typical and maximum current consumptions in stop mode . added crypto, rng, and hash consumption in table 23: peripheral current consumption . updated md minimum value in table 33: sscg parameters constraint . added examples in section 5.3.11: pll spread spectrum clock generation (sscg) characteristics . updated table 51: spi characteristics and table 52: i2s characteristics . updated figure 44: ulpi timing diagram and table 58: ulpi timing . updated table 60: dynamics characteristics: ethernet mac signals for smi , table 61: dynamics characteristics: ethernet mac signals for rmii , and table 62: dynamics characterist ics: ethernet mac signals for mii . updated maximum f s values in table 63: adc characteristics . section 5.3.25: fsmc characteristics : updated ta bl e 6 9 to ta b l e 8 0 , changed c l value to 30 pf, and modified fsmc configuration for asynchronous timings and waveforms. updated figure 58: synchronous multiplexed psram write timings . updated table 81: dcmi characteristics . updated table 88: ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm mechanical data . table 92. document revision history (continued) date revision changes
stm32f21xxx revision history doc id 17050 rev 8 169/173 20-dec-2011 6 (continued) appendix a.3: usb otg full speed (fs) interface solutions : updated figure 84: usb otg fs (full speed) host-only connection and added note 2 , updated figure 85: otg fs (full speed) connection dual-role with internal phy and added note 3 and note 4 , modified figure 86: otg hs (high speed) device connection, host and dual-role in high- speed mode with external phy and added note 2 . appendix a.4: usb otg high speed (hs) interface solutions : removed figures usb otg hs device-only connection in fs mode and usb otg hs host-only connection in fs mode, updated figure 86: otg hs (high speed) device connection, host and dual-role in high- speed mode with external phy . added appendix a.6: ethernet interface solutions . updated disclaimer on last page. table 92. document revision history (continued) date revision changes
revision history stm32f21xxx 170/173 doc id 17050 rev 8 24-apr-2012 7 updated number of usb otg hs and fs, added note 1 related to fsmc and note 3 related to spi/i2s in table 2: stm32f215xx and stm32f217xx: features and peripheral counts . added note 2 and update tim5 in figure 4: stm32f21x block diagram . updated maximum number of maskable interrupts in section 2.2.10: nested vectored interrupt controller (nvic) . removed stm32f215xx in section 2.2.28: universal serial bus on- the-go full-speed (otg_fs) . removed support of i2c for otg phy in section 2.2.29: universal serial bus on-the-go high-speed (otg_hs) . removed otg_hs_scl, otg_hs_sda, otg_fs_intn in table 5: stm32f21x pin and ball definitions and table 7: alternate function mapping . ph10 alternate function tim5_ch1_etr renamed tim5_ch1. added table 6: fsmc pin definition . updated v por/pdr in table 16: embedded reset and power control block characteristics . updated v dda and v ref+ decouping capacitor in figure 16: power supply scheme . updated typical values in table 21: typical and maximum current consumptions in standby mode and table 22: typical and maximum current consumptions in vbat mode . updated table 27: hse 4-26 mhz oscillator characteristics and table 28: lse oscillator char acteristics (flse = 32.768 khz) . updated table 34: flash memory characteristics , table 35: flash memory programming , and table 36: flash memory programming with vpp . updated section : output driving current . updated note 3 and removed note related to minimum hold time value in table 49: i2c characteristics . updated table 61: dynamics characteristics: ethernet mac signals for rmii . updated c adc , i vref+ , and i vdda in table 63: adc characteristics . updated note concerning adc accuracy vs. negative injection current below table 64: adc accuracy . updated figure 81: ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm, package outline . appendix a.1: main applications versus package : removed number of address lines for fsmc/nand in table 91: main applications versus package for stm32f2xxx microcontrollers . appendix a.5: complete audio player solutions : updated figure 87: complete audio player solution 1 and figure 88: complete audio player solution 2 . table 92. document revision history (continued) date revision changes
stm32f21xxx revision history doc id 17050 rev 8 171/173 29-oct-2012 8 removed figure 4. compatible board design between stm32f10xx and stm32f2xx for lqfp176 package. updated number of ahb buses in section 2: description and section 2.2.12: clocks and startup . updated note 2 below figure 4: stm32f21x block diagram . changed system memory to system memory + otp in figure 13: memory map . added note 1 below table 13: vcap1/vcap2 operating conditions . updated v dda and v ref+ decouping capacitor in figure 16: power supply scheme and updated note 3 . changed simplex mode into half-duplex mode in section 2.2.24: inter- integrated sound (i2s) . replaced dac1_out and dac2_out by dac_out1 and dac_out2, respectively. changed tim2_ch1/tim2_etr into tim2_ch1_etr for pa0 and pa5 in table 7: alternate function mapping . updated note applying to i dd (external clock and all peripheral disabled) in table 17: typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator disabled) . updated note 3 below table 19: typical and maximum current consumption in sleep mode . removed f hse_ext typical value in table 25: high-speed external user clock characteristics . updated master i2s clock jitter conditions and vlaues in ta b l e 3 2 : plli2s (audio pll) characteristics . updated equations in section 5.3.11: pll spread spectrum clock generation (sscg) characteristics . swapped ttl and cmos port conditions for v ol and v oh in ta b l e 4 4 : output voltage characteristics . updated v il(nrst) and v ih(nrst) in table 46: nrst pin characteristics . updated table 51: spi characteristics and table 52: i2s characteristics .removed note 1 related to measurement points below figure 39: spi timing diagram - slave mode and cpha = 1 , figure 40: spi timing diagram - master mode , and figure 41: i2s slave timing diagram (philips protocol)(1) . updated t hc in table 58: ulpi timing . updated figure 45: ethernet smi timing diagram , table 60: dynamics characteristics: ethernet mac signals for smi and table 61: dynamics characteristics: ethernet mac signals for rmii . update f trig in table 63: adc characteristics . updated i dda description in table 65: dac characteristics . updated note below figure 50: power supply and reference decoupling (vref+ not connected to vdda) and figure 51: power supply and reference decoupling (vref+ connected to vdda) . replaced t d(clkl-noel) by t d(clkh-noel) in table 73: synchronous multiplexed nor/psram read timings , table 75: synchronous non- multiplexed nor/psram read timings , figure 57: synchronous multiplexed nor/psram read timings and figure 59: synchronous non-multiplexed nor/psram read timings . table 92. document revision history (continued) date revision changes
revision history stm32f21xxx 172/173 doc id 17050 rev 8 29-oct-2012 8 (continued) added figure 80: lqfp176 recommended footprint . added note 2 below figure 82: regulator off/internal reset on . updated device subfamily in table 90: ordering information scheme . remove reference to note 2 for usb iotg fs in ta b l e 9 1 : m a i n applications versus package for stm32f2xxx microcontrollers . table 92. document revision history (continued) date revision changes
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